The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow. The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More
CEO Interview with Rabin Sugumar of AkeanaRabin Sugumar was Distinguished Engineer and Chief Architect…Read More
Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation Verification Futures Conference 2025…Read More
2026 Outlook with William Wang of ChipAgents.aiWilliam Wang is a world-leading expert in artificial…Read More
Silicon Catalyst: Searching for the Next Great Start-upSilicon Catalyst has emerged as a distinctive force…Read MoreNoose tightens on SMIC- Dead Fab Walking?
-US Administration to “blacklist” SMIC- Cutting off ALL US help
-A slow death versus a quick death (unlike Jinhua)
-There is enough time on way out door to leave scorched earth
-Reports in the Media about SMIC being “Blacklisted”
It has been widely reported that SMIC will be added to the US “Blacklist”… Read More
PLDA Brings Flexible Support for Compute Express Link (CXL) to SoC and FPGA Designers
A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™. The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More
ML plus formal for analog. Innovation in Verification
Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.
The Innovation
This month’s pick… Read More
Applied Materials Will Regain Semiconductor Equipment Lead From ASML in 2020
On December 2, 2019, I posted a SemiWiki article entitled “ASML Will Take Semiconductor Equipment Lead from Applied Materials in 2019.”Since losing its dominance for the first time since 1990 in 2019, Applied Materials is poised to lose its retake the 2020 lead in the semiconductor equipment market. ASML led the… Read More
CD-Pitch Combinations Disfavored by EUV Stochastics
Ongoing investigations of EUV stochastics [1-3] have allowed us to map combinations of critical dimension (CD) and pitch which are expected to pose a severe risk of stochastic defects impacting the use of EUV lithography. Figure 1 shows a typical set of contours of fixed PNOK (i.e., the probability of a feature being Not OK due… Read More
Webinar: 5 Reasons Why Others are Adopting Hybrid Cloud and EDA Should Too!
With the complexity of transistors at an all time high and growing foundry rule decks, fabless companies consistently find themselves in a game of catch up. Semiconductor designs require additional compute resources to maintain speed and quality of development. But deploying new infrastructures at this current speed is a tall… Read More
Low Power SRAM Register Files for IoT, AI and Wearables
SRAM is the workhorse for on-chip memories, valued for its performance and easy integration with standard processes. The needs of wearable, IoT and AI SOCs have put a lot of pressure on the requirements for all on-chip memories. This is perhaps most evident in the area of power. AI chips that rely heavily on SRAM register files are… Read More
Folding at Home. The Ultimate in Parallel Acceleration
You may have heard of Folding at Home. It’s a very creative way that a bioengineering team, based at Washington University in St Louis, are modeling the process of protein folding. Greg Bowman, an associate professor of biochemistry and biophysics at the university directs the project and presented at Arm DevSummit this year. … Read More
China Semiconductor Bond Bust!
– Tsinghua $198M Bond Bust
– Good for memory: Samsung Micron LG Toshiba –
– Not good for chip equipment
– Could China Credit Crunch hit more than foundry embargo?
– Damage to China memory positive for other memory makers
– Not good for chip equip if customers can’t get money
China’s… Read More



CES 2026 and all things Cycling