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CDC, Low Power Verification. Mentor and Cypress Perspective

CDC, Low Power Verification. Mentor and Cypress Perspective
by Bernard Murphy on 01-13-2021 at 6:00 am

CDC Low Power

Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More


ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right
by Mike Gianfagna on 01-12-2021 at 10:00 am

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

The Electronic System Design (ESD) Alliance (a SEMI Technology Community) recently released their regular report on EDA revenue for Q3, 2020 . While the report is a normal occurrence, the numbers in this particular report are anything but normal. I have been reviewing these reports for many years, and I honestly can’t remember… Read More


The Latest in Dielectrics for Advanced Process Nodes

The Latest in Dielectrics for Advanced Process Nodes
by Tom Dillinger on 01-12-2021 at 6:00 am

new ILDs v2

Of the three types of materials used in microelectronics – i.e., semiconductors, metals, and dielectrics – the first two often get the most attention.  Yet, there is a pressing need for a rich variety of dielectric materials in device fabrication and interconnect isolation to satisfy the performance, power, and reliability … Read More


Achronix Speedster7t Garners Best Practices Award for FPGA

Achronix Speedster7t Garners Best Practices Award for FPGA
by Tom Simon on 01-11-2021 at 10:00 am

Frost and Sullivan 2020 Award Achronix

FPGAs have played an important role in the growth of key markets, including networking, storage, mobile devices, etc. They offer a unique set of capabilities that ASICs, CPUs and GPUs find hard to match. FPGAs are wire-speed, programmable integrated circuits that accelerate data and applications.  The ability to reprogram … Read More


Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design

Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design
by Mike Gianfagna on 01-11-2021 at 6:00 am

Webinar Rescale is Providing an On Ramp to the Hybrid Cloud for Chip Design

We all know that design complexity is increasing at a fast pace. There’s always more analysis to run on larger and larger volumes of data. During tapeout, these demands can grow by an order of magnitude. Successful design projects need to add huge amounts of CPU, memory and storage for short bursts of time during tapeout to meet their… Read More


Car Wars 2021

Car Wars 2021
by Roger C. Lanctot on 01-10-2021 at 10:00 am

Car Wars 2021

A strange narrative took hold in the U.S. at the end of 2020 that vehicle sales were in decline, that cars weren’t selling. The reality is something quite different. In spite of nearly two solid months of auto factory and dealership shutdowns, automotive sales surged back in 2020 – a phenomenon that manifested globally with regional

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The Complexities of the Resolution Limits of Advanced Lithography

The Complexities of the Resolution Limits of Advanced Lithography
by Fred Chen on 01-10-2021 at 6:00 am

The Complexities of the Resolution Limits of Advanced Lithography

For advanced lithography used to shrink semiconductor device features according to Moore’s Law, resolution limits are an obvious consideration. It is often perceived that the resolution limit is simply derived from a well-defined equation, but nothing can be further from the truth.

Optical Lithography: the fine print

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Podcast EP2: Moore’s Law, Dead or Alive?

Podcast EP2: Moore’s Law, Dead or Alive?
by Daniel Nenni on 01-08-2021 at 10:00 am

Dan and Mike are joined by Dr. Walden Rhines for a scenic tour of Moore’s Law. The genesis and evolution of Moore’s Law are discussed, along with the fundamental processes that have driven it. How the technology world continues to grow and innovate in spite of a slowing of Moore’s Law is a central theme of the discussion.… Read More


IEDM 2020 – Imec Plenary talk

IEDM 2020 – Imec Plenary talk
by Scotten Jones on 01-08-2021 at 6:00 am

Imec Figure 1

On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More


The Growing Chasm in Electronic System Design

The Growing Chasm in Electronic System Design
by Rahul Razdan on 01-07-2021 at 10:00 am

supply chain block diagram

Since the formation of the Electronic Design Automation (EDA) industry in the 1970s, Moore’s law has increased functionality onto a semiconductor die dramatically.  In response,  EDA tools for semiconductor design have also grown in functionality and the design processes for semiconductors have moved forward at a breakneck… Read More