At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was the very personable Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys. Henry currently leads engineering for 3DIC, advanced technology and visualization.
TSMC’s 3DFabric initiative was a big focus at the symposium, as it should be. I remember when TSMC first went public with CoWos the semiconductor ecosystem, including yours truly, let out a collective sigh wondering why TSMC is venturing into the comparatively low margin world of packaging. Now we know why and it is absolutely… Read More
At SemiWiki we’ve written four times now about how TSMC is standardizing on a 3DIC physical flow with their approach called 3Dblox, so I watched a presentation from John Ferguson of Siemens EDA to see how their tool flow supports this with the Calibre tools. With a chiplet-based packaging flow there are new physical verification… Read More
If, like me, you’ve been paying too little attention to historically less glamorous areas of chip design like packaging, you’ll wake up one day and realize just how much things have changed and continue to advance and how interesting it’s become.
One of the main drivers here is the increasing use of chiplets to counter the decreasing… Read More
On November 10th I watched the presentation by L.C. Lu, TSMC Fellow & VP, as he talked about enabling system innovation with dozens of slides in just 26 minutes. TSMC is the number one semiconductor foundry in the world, and their Open Innovation Platform (OIP) events are popular and well attended as the process technology and… Read More
This was the 12th TSMC OIP and it did not disappoint. The attendance was back to pre pandemic levels, there was interesting news and great presentations. We will cover the presentations in more depth after the virtual event which is on November 10th. You can register HERE.
As I mentioned in my previous post, the Jim Keller Keynote … Read More
One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.
In my 40 years as a … Read More
TSMC recently held their annual Technology Symposium in Santa Clara, CA. The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development. This article will summarize the highlights of the advanced packaging… Read More
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The Chip 4: A Semiconductor Elite