Security Coverage: Assuring Comprehensive Security in Hardware DesignAs hardware systems become increasingly complex and security…Read More
Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC3D IC was a very popular topic at…Read More
Analysis and Exploration of Parasitic EffectsWith advanced semiconductor processes continuing to shrink, the…Read More
Siemens Proposes Unified Static and Formal Verification with AIGiven my SpyGlass background I always keep an…Read More
Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 RoadmapAlchip Technologies, a global leader in high-performance computing…Read More
Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight… Read More
Ten years ago the Open Mobile Video Coalition was touting its plans to deliver free over-the-air television to mobile devices and automobiles. At the time, OMVC was seen as the realization of a dream of delivering video to cars – front seat and back.
The dream didn’t last long and the plans for ATSC M/H brought to the market by the OMVC… Read More
On my flight to Las Vegas for the annual Consumer Electronics show I dug in to Jeff Smulyan’s autobiographical “Never Ride a RollerCoaster Upside Down – The Ups and Downs and Reinvention of an Entrepreneur.” As CEO, Chairman, and Founder of Emmis Communications Smulyan has had a front row seat to the evolution of the electronics… Read More
As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. And don’t forget to come see us at DVCon,… Read More
At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.
Logic designs are built up by standard cells such as inverters,… Read More
The pursuit of ever smaller DRAM cell sizes is still active and ongoing. DRAM cell size is projected to approach 0.0013 um2 for the D12 node. Patterning challenges are significant whether considering the use of DUV or EUV lithography. In particular, ASML reported that when center-to-center values reached 40 nm, single patterning… Read More
The semiconductor ecosystem has been full of interesting twists of late and Alphawave has been a company to watch since the very beginning. Alphawave came out of stealth mode in early 2019 as the world’s first IP company focused on multi-standard connectivity (SerDes) IP solutions. The importance of SerDes had been understated… Read More
-UCTT & ICHR both pre announce ugly QTR & blame memory
-LRCX is the memory “poster child” & most impacted
-This is on top of China & Economic issues & memory specific
-Clearing out inventory is a sign of expected slow recovery
Both UCTT & ICHR that … Read More
The first Chiplet specific conference is coming up which is a milestone in itself. As we know the only thing new about chiplets is the name but when there is a dedicated conference to such a specific thing you know it has officially “arrived”. There is even a cool new tagline: Chiplets make huge chips happen!
“The First Annual Chiplet… Read More
Dan is joined by Lu Dai who is currently a Senior Director of Technical Standards at Qualcomm. Previously he was Senior Director of Engineering, leading Qualcomm’s SoC design verification team and front-end methodologies and initiatives. Lu is Chair of Accellera Systems Initiative and serves on the Board of Directors at RISC-V… Read More
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cHBM for AI: Capabilities, Challenges, and Opportunities