Banner 800x100 0810

Design for Manufacturability Analysis for PCB’s

Design for Manufacturability Analysis for PCB’s
by Tom Dillinger on 09-29-2017 at 7:00 am

Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finerRead More


Emulation Methodology for Drones and Other Video-Intensive Multimedia SoCs

Emulation Methodology for Drones and Other Video-Intensive Multimedia SoCs
by Richard Pugh on 09-28-2017 at 12:00 pm

What do drones, augmented reality devices, and 4K UHD TV have in common? They all include complex system-on-chips (SoCs) that must encode and decode, in real-time, data for increasingly higher definition video content. Verifying that these SoC designs are functionally correct is quite complex, but they must also function efficiently… Read More


High-Speed Equivalence Checking

High-Speed Equivalence Checking
by Bernard Murphy on 09-28-2017 at 7:00 am

Following on product introductions for simulation and prototyping, physical verification and implementation earlier in the year, Anirudh Devgan (Exec VP and GM at Cadence), the king of speed and parallelism has done it again, this time with logic equivalence checking (LEC). Cadence recently announced an advance to their well-known… Read More


Portable Stimulus Standard, What’s New from Cadence

Portable Stimulus Standard, What’s New from Cadence
by Daniel Payne on 09-27-2017 at 12:00 pm

I’ve been hearing about the Portable Stimulus Standard (PSS) since DAC 2016, so it’s helpful to get an update from EDA vendors on what their involvement level is with this emerging standard and how they see it helping design and verification engineers. Earlier in September I scheduled a conference call with Cadence… Read More


CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics

CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics
by Mitch Heins on 09-27-2017 at 7:00 am

I had the pleasure of being able to attend the CDNLive event held in the Boston, MA area last month and I was pleasantly surprised to see that Cadence highlighted Silicon Photonics as one of its Keynote topics. MIT Professor Duane Boning gave an excellent overview of the current state of silicon photonics and why he believes it is time… Read More


How to Avoid Jeopardizing SoC Security when Implementing eSIM?

How to Avoid Jeopardizing SoC Security when Implementing eSIM?
by Eric Esteve on 09-26-2017 at 12:00 pm

Smart card business is now more than 25 years old, we can assess that the semiconductor industry is able to protect the chips used for smart card or SIM application with a very good level (unfortunately, it’s very difficult to get access to the fraud percentage linked with smart cards, as bankers really don’t like to communicate on… Read More


Verification Trends: 2016

Verification Trends: 2016
by Bernard Murphy on 09-26-2017 at 7:00 am

Periodically Mentor does us all a big favor by commissioning a survey of verification engineers across the world to illuminate trends in verification. This is valuable not only to satisfy our intellectual curiosity but also to help convince managers and finance mandarins that our enthusiasm to invest in new methods and tools … Read More


Robust NVM Solutions for Specialty and Advanced FinFET Technologies Webinar

Robust NVM Solutions for Specialty and Advanced FinFET Technologies Webinar
by Daniel Nenni on 09-25-2017 at 12:00 pm

Webinars are a very effective communications channel in a fast paced industry like semiconductor design. If you sign-up in advance and you can’t make the live version, you will be automatically notified when the replay is available so you can watch it at your leisure. I’m guilty of this for sure, because of my hectic… Read More