Staff RTL Design Engineer – Cache Subsystem

Job Description:

The Role

As a Cache Subsystem Microarchitect and RTL design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

• You will architect, design and implement new high performance cache subsystems in SiFive’s RISC-V CPU core generators and enhance features and performance in existing ones.
• Work on the microarchitecture development and specification; ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
• Perform initial sandbox verification and work closely with the verification team to create and execute detailed verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Collaborate with the performance modelling team for performance exploration and optimization to meet performance goals.

You will have:

• At least five years of relevant industry experience working on high-performance, energy-efficient cache subsystem designs, ideally within a CPU or GPU subsystem.
• A background of successful cache subsystem development from architecture through to tapeout.
• Expertise in multi-level coherent cache architectures and designs.
• Experience with TileLink or other similar interconnect architecture.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• A Bachelor’s or Master’s degree in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice to have:

• Knowledge of RISC-V architecture.
• Experience with Scala and/or Chisel.
• Understanding of IP verification tools and methodologies such as UVM and Formal.
• Knowledge of at least one object-oriented and/or functional programming language.

If you want to do incredible work and be challenged by exciting, truly innovative projects that will test the boundaries of your skills and creativity, then SiFive is the place for you!  Be proud of your work.  Do things better.  Join SiFive