Staff Engineer, SerDes and IP RTL

Primary Responsibilities:

The employee will be responsible for block-level IP RTL design as well as full chip-level integration RTL design for Achronix’s FPGA products. The employee is expected to take independent ownership of complex design challenges, which may include:

• Micro-architecture development
• RTL code development
• Timing constraints development with STA team
• Performance modeling
• Post-Si bring-up
• Automation development for FPGA specific IP generation

The employee is also expected to participate regularly in interactions with global teams spanning System Engineering, Software, and Product Engineering

Skills:

• Expertise in micro-architecture development and RTL coding
• Strong knowledge of Network protocols (PCIE or Ethernet) is a must. Should be able to validate third-party IPs for performance/area and SoC integration
• Hands-on experience in integrating/Validating System interconnect (AXI interconnect) is a plus
• Strong knowledge of DDR/GPIO PHYs and memory controllers is a plus
• Experience with system level performance modeling is a plus
• Experience with post-Si bring-up and debug is a plus
• Experience with synthesis and STA is a plus
• Automation and scripting experience
• Excellent verbal and written communication skills
• Ability to work in a dynamic and fast-paced environment with a proactive mindset

Experience/Education:

• Preferred BS/MS and 6-12 years of experience in RTL design and verification
• Previous experience in at least 2-3 product developments including post-Si bring-up