Staff Engineer, Physical Design – High Speed Interconnects

Job Description:

About the Role –

As a Staff Physical Design Engineer (High-Speed Interconnects), you will be responsible for the end-to-end implementation of high-bandwidth Network-on-Chip (NoC) and Uncore subsystems.

This is not a traditional “siloed” backend role; you will operate at the intersection of architecture, design and physical implementation. You will drive PPA (Power, Performance, Area) outcomes by influencing RTL structures and floorplanning strategies early in the design cycle. Your expertise in advanced process nodes and system-level data flow will be critical in delivering scalable, high-frequency IP that forms the backbone of our next-generation compute platforms.

Responsibilities – What You’ll Do

• End-to-End Implementation: Execute the full physical design flow (RTL-to-GDSII) for complex NoC and Uncore subsystems, ensuring timing closure and routability for interconnects.
• Architecture & PD Co-Design: Partner with RTL and Architecture teams to perform early-stage feasibility analysis. Identify physical bottlenecks in the microarchitecture and propose RTL restructuring, such as optimized pipelining or bus-width adjustments, to meet PPA targets.
• Advanced Floorplanning: Own hierarchical partitioning and macro placement. You will define the physical blueprint for massive die areas, optimizing pin assignments and global routing tracks to minimize latency across the fabric.
• Interconnect Problem Solving: Solve unique NoC challenges, including long-wire RC compensation, repeater strategy for global signals, and complex clock/reset distribution across hierarchies.
• Methodology Innovation: Develop and refine automated flows for hierarchical implementation. You will identify gaps in existing scripts and tools to improve turnaround time and design quality across multiple technology nodes.
• Technical Mentorship: Provide technical guidance to mid-level engineers, leading design reviews and establishing best practices for high-performance physical implementation.

Requirements – What You’ll Bring

• Deep Experience: 7+ years of hands-on physical design experience, with a proven track record of closing complex blocks or subsystems on FinFET nodes (7nm and below).
• Systems-Level Mindset: Understanding of NoC designs. You should be comfortable navigating RTL and understanding how logic structures translate to physical layout.
• Hierarchical Expertise: Proven ability to manage top-level integration, including budget constraints, hierarchical P&R and timing closure.
• Tool Mastery: Expert-level proficiency with industry-standard EDA suites – Synopsys and/or Cadence implementation and sign-off tools.
• Analytical Rigor: A data-driven approach to PPA tradeoff optimization; accompanied by a detail-oriented mindset and clear communication.
• Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field.

Why Join Us?

• Be part of the RISC-V movement and help define the future of computing architecture.
• Work on industry-leading IP adopted by top customers and shipped in high volumes worldwide.
• Collaborate with world-class engineers in a supportive, fast-paced, learning environment.
• Enjoy a culture that values innovation, ownership, and technical excellence.
• Our large IP portfolio offers opportunities to engineer solutions across multiple IPs and product families over time.