Sr. Eng Design Enablement – SiV Validation Engineer – Design Manuals

We are looking for the candidate to work on the development of advanced technology nodes, FD-SOI and FinFET, within a dynamic team of semiconductor development experts. This position involves activities associated with the development of energy efficient, ultra-low power and ultra-low leakage technologies for emerging products in IoT, Mobile, and RF/5G applications. Selected candidate will work closely with Dresden FAB1 Technology Development teams to understand and validate technology design rules (TDR), electrical design rules (EDR) as well as with process integration, yields engineers to understand and validate prevalent process/design driven fail modes in order to define and design highly automatable and reusable electrical test structures. Selected candidate will be working on advanced technology nodes (14nm and below) and must have detailed understanding of both planar and 3-D devices.

Specific Responsibilities:

• Work with Technology Enablement, Design rule development, Process integration and Yield engineering teams to understand and validate technology design rules and systematic design-process interaction driven fail modes
• Define and design experimental electrical DOE test structures to assess design and process weak points in order to ensure design rule/PDK and process flow robustness
• Perform detailed Si validation analysis for the process bring-up at the manufacturing facility. Analyze test structure data to investigate systematic design driven yield and performance detractors, followed by root cause analysis and understanding
• Compile Si validation reports and communicate Si analysis results to the multiple design and process development engineering teams
• Drive Si validation of critical process and design fail modes to ensure product manufacturability and customer satisfaction

Required Qualifications:

• BSEE in Electrical Engineering, Materials Science, Solid State Physics, or other relevant engineering discipline.
• Minimum of 6 years of semiconductor industry experience in solid state and semiconductor device, or process integration or unit process development areas required
• Understanding of semiconductor process fabrication flow, nanofabrication, solid state and semiconductor device physics and design of experiments (DOE) methodology
• Familiarity with semiconductor physical design including electrical test structure design
• Familiarity with EDA tools such as Cadence Virtuoso Virtuoso Schematic Editor, Virtuoso Layout Suite, Calibre (DRC, LVS)
• Strong data analysis, data mining and problem solving skills. Experience with statistical data analysis packages like SAS JMP.
• Excellent written and oral communications skills
• Strong interpersonal skills; team player; able to work effectively in a dynamic, fast paced environment
• Demonstrated ability to meet deadlines and commitments

Preferred Qualifications:

• MS in Electrical Engineering, Electrical Computer, Solid State Physics, Materials Science, or other relevant engineering discipline plus 3-5 years of Semiconductor industry experience in device, process integration or unit process areas preferred
• PhD in Electrical Engineering, Electrical Computer, Solid State Physics, Materials Science, or other relevant engineering discipline plus 0-2 years of Semiconductor industry experience in device, process
• Hand-on processes integration, device or design experience in advanced technology nodes such 22nm or 28nm FDSOI technology, 14nm and below FINFET technology
• Strong hand-on semiconductor physical design experience including electrical test structure design
• Strong hand-on experience with EDA tools such as Cadence Virtuoso Virtuoso Schematic Editor, Virtuoso Layout Suite, Calibre (DRC, LVS)
• Solid understanding on process and design layout interaction, FMEA methodology
• Design for manufacturing experience and Programming skills in Perl, TCL, or Python are desirable