SPE Analog Engineering

The candidate will be part of Rambus Memory Interface Chips BU’s design group responsible for specifying, architecting, executing, and productizing leading edge memory interface buffer chips for DDR5, DDR6 and beyond.   

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.  

• Owner and domain expert of analog and mixed signal designs at chip and block level, especially for high-speed data receivers 
• Architect, design, simulate and characterize high-performance and low-power high-speed circuits including receiver, samplers, and signal conditioning circuits 
• Modeling of chip and block level at various levels of detail for design tradeoff analysis and voltage and timing budgeting  
• Supervise analog layout engineering to ensure attention to detail on high performance analog layout for critical IO blocks  
• Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution  
• Other responsibilities include layout supervision, design documentation, guiding and debugging post-silicon validation, correlating silicon to simulation 

• MSEE/Ph.D. with 10+ years of analog / mixed-signal circuit design experience  
• Must have understanding of SI/PI principles and interaction with receiver front-end principles 
• Direct chip design experience in DDR interface design is a strong plus  
• Experience with Verilog coding is a strong plus  
• Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices.