Senior Hardware Engineer – Micro-Architect

The Opportunity

This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.

Our preference is for a candidate located in the California Bay Area who can regularly collaborate from our Burlingame office.

From time to time, the team and company gather for onsite meetings and offsite events. These in-person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.

What You’ll Do

• Contribute to the definition of the processor architecture by understanding its applications
• Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
• Own Power, Performance & Area (PPA) optimization
• Contribute to timing closure through full product cycle (front end, back-end, tapeout)

What Success Looks Like

Within your first 6–12 months, you’ll:

• Independently own a major design block and improve PPA
• Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
• Package design for customer releases and incorporate customer feedback

What We’re Looking For

Required

• BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
• Proficiency in SystemC, SystemVerilog, or Verilog
• Strong background in computer architecture
• Knowledge of design techniques for low power digital design
• Knowledge of VCS & Verilog/C Co-Sim
• Experience in data-parallel hardware design for high-performance computing
• Experience in FPGA design is a plus
• Experience in logic synthesis and performance modeling

Preferred

• Experience marketing semiconductor IP, AI accelerators, SoCs, EDA tools, or developer platforms.
• Familiarity with automotive safety (ASIL) standards

What We Offer

The base salary range for this position is $150,000 to $220,000. This range reflects the full span of levels and geographies at which Quadric hires for this role. The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. In addition to base salary, this role is eligible for equity and a discretionary annual performance bonus as applicable to the role and level.

In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our US-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:

• Medical, dental, and vision insurance from day one – Premiums covered at 99% for Employees
• Company-paid life Insurance
• Voluntary supplemental life insurance
• STD + LTD insurance
• Commuter support including parking or Caltrain reimbursement. Our office is conveniently located within walking distance of the Caltrain station
• FSA + HSA
• Equity with the business
• Paid Parental Leave
• 401(k) Retirement Plan
• Flexible PTO
• Winter holiday shutdown
• Catered lunch each day in our office
• Downtown Burlingame office location, close to shops, cafes, and local amenities
• Collaborative, low-ego culture with significant ownership and impact
• A work culture focused on innovative disruption