RTL SoC Design Intern

The Opportunity

This is a chance to get hands-on experience building a next-generation SoC architecture from the ground floor, working directly alongside our hardware team as we bring supercomputer technology to the Edge.

You’ll support the SoC design team with subsystem development, third-party IP integration, and PPA (power, performance, area) optimization for Quadric’s GPNPU platform — gaining exposure to real front-end design and integration methodologies, and working closely with the architects who define the chip.

Note: Our preference is for this internship to be based out of our Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period and available to work on site.

What You’ll Do

Support SoC Subsystem Development

• Help design and integrate SoC-level subsystems, working alongside engineers integrating third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
• Contribute to documentation of SoC architecture and application requirements.

Support PPA Optimization

• Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
• Get exposure to low-power digital design techniques and timing closure work across front-end stages.
• Collaborate Across the Team
• Work closely with SoC architects and designers to understand design intent and integration requirements.
• Communicate findings, blockers, and technical questions clearly to the team.

What Success Looks Like

Within your internship, you’ll:

• Build a working understanding of SoC subsystem development and integration.
• Contribute analysis or documentation that meaningfully supports PPA optimization efforts.
• Develop hands-on fluency with SystemVerilog or Verilog in a real front-end design environment.

What We’re Looking For

Required

• Currently pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Preferred

• Coursework or project experience with computer architecture, low-power design, or RTL design.
• Exposure to logic synthesis, FPGA design, or performance modeling.
• Adept with scripting languages like Python and using LLMs to get things done

What We Offer

The hourly salary range for this temporary position is $50-57/hr . This range reflects the full span of levels and geographies at which Quadric hires for this role. The actual hourly salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies.

Quadric interns receive hands-on experience working alongside industry experts in AI and semiconductor technology, with access to mentorship and meaningful project ownership from day one along with following

• Catered lunch each day in our office
• Downtown Burlingame office location, close to shops, cafes, and local amenities
• A work culture focused on innovative disruption

If this role resonates with you, we encourage you to apply even if your experience does not perfectly match every qualification. We value potential, curiosity, and a willingness to learn just as much as direct experience.