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R&D SW Engineer

R&D SW Engineer
by Admin on 03-16-2020 at 10:57 pm

Website Siemens EDA

Design verification at RTL level is critical for time to market and various innovative ways are needed for faster verification. Emulation based verification had been grown significantly over years due to increase in design size and various verification complexity in all domain being functional validation, power verification/ estimation and most important performance. Extended verification complexity is needed to do shift left in verification area. Performance plays a significant role in emulation based validation to make sure design verification is done in time.

Mentor emulation platform Veloce leads solving above challenges in all domains.
The person in this role will be responsible for developing, enhancing and maintaining key technology components of the RTL Compiler (frontend RTL Synthesis for Veloce) of Mentor Graphics in verification domain. The candidate should have experience in EDA software, preferably in the RTL synthesis domain.
  • Develop key software components with high quality results on RTL synthesis.
  • Work on various RTL Synthesis optimizations as wells as on technology mapping flow
  • Independently test, benchmark and fix issues in synthesis.
  • Identify and work on potential improvements and optimizations.
  • Extend and maintain the functionality of the RTL Compiler as needed.
  • Write technical specs and participate in technical discussions, code reviews.
  • Work with the team to jointly solve technical problems and within given deadline.
  • B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college like the I.I.Ts.
  • 4+ years of relevant experience in EDA tool development. Experience with RTL synthesis tools is a plus.
  • Should have good knowledge of C/C++, data structures and algorithms.
  • Should have worked on large software projects and be familiar with software development processes.
  • Good knowledge of memory and performance considerations in software design.
  • Working knowledge of Verilog/VHDL, synthesis, simulation.
  • Working knowledge of RTL synthesis especially in the area of optimization is plus
  • Self-motivated individual and willing to learn and contribute in a global team.

Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time

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