Principal Design Engineer

Tensilica IP division of Cadence is looking for an experienced and motivated engineer to join our systems modeling team in Noida. The candidate will work on extending and improving the product portfolio and the existing solution to the customers which includes Instruction Set Simulator (ISS) for various DSPs, software tools and other components to the customers. Key responsibilities include:

• Development and verification of system models for HW accelerators and other SoC components that accompany Tensilica processor cores.
• Close collaboration with the ISS and tools teams to improve the entire system modelling product offering.
• Integration of the Xtensa ISS and other models with 3rd party system modeling environments.
• Regular interaction with marketing, field and customers to understand and promptly address their problem reports and enhancement requests.

Requirements:

• Degree (Masters/Bachelor or equivalent) in Computer/Electrical Engineering or related field.
• 6+ years of industry experience in research or development of system modeling, processor simulation or architecture exploration.
• Strong in system level model development using C/C++, SystemC/TLM.
• Deep understanding of processor architectures, bus protocols such as AXI, ACE.
• Desirable to have experience with modeling tools for performance analysis or hardware/software co-simulation.
• Excellent problem solving and analytical skills.
• Strong communication and teamwork skills.