Layout Designer

In R&D, Design and Technology Platform (DTP) provides differentiated and world-leading design solutions to enable the implementation of System on Chip (SoC) for leading AI/HPC, communication, automotive and IoT applications on TSMC’s diverse silicon and packaging technology platform. We work with the world’s leading SoC design teams and ecosystem experts to promote industry-leading process design kits (PDKs) and reusable design blocks for the semiconductor intellectual property core (IP), including standard cell libraries, embedded memory, general-purpose input/output (GPIO), simulation and interface IP, as well as electronic design automation (EDA) tools and design flows for monolithic SoCs and heterogeneous 3DICs. This allows us to accelerate the process of transforming innovation into silicon chips and creating revolutionary changes in daily life!

Job Responsibilities

1. Support Layout production and quality verification for advanced node.
2. Advanced node path finding for best speed, power and area by using layout technique.
3. Methodology development for layout optimization, productivity and quality enhancement.
4. Machine Learning/AI exploratory for layout quality and productivity enhancement.

Job Qualifications

1. Ph.D or Master degree in Electrical Engineering/Computer engineering.
2. Good knowledge of basic circuits and logic design.
3. Knowledgeable in major custom design EDA tools.
4. Experience on layout project is preferred.