ASIC Digital Design, Staff Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature and other monitoring IPs within SOC subsystem. Synopsys is the market leader for these IP developments which are integral parts of Silicon lifecycle monitoring.

You Are:

As a new, exciting and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based on improved monitoring capacity and forward-looking project schedules.

What You’ll Be Doing:

• Generate test benches and test cases.
• Perform RTL and gate-level SDF-annotated simulations and debug.
• May perform mixed-signal (digital + analog) simulations and debug.
• Interact with our application engineers and provide guidance to customers.
• Participate in the generation of data books, application notes, and white papers.
• Contribute to enhance quality assurance methodology by adding more quality checks/gatings.
• Perform physical verification and design rule checks to ensure design integrity and manufacturability.

The Impact You Will Have:

• Enhance the quality and reliability of our PVT Sensor IPs.
• Improve project forecasting and monitoring capabilities.
• Support the development of innovative solutions for chip design and verification.
• Strengthen customer relationships through effective guidance and support.
• Contribute to knowledge sharing through documentation and training materials.
• Drive continuous improvement in design methodologies and tools.

What You’ll Need:

• Bachelor’s or master’s degree in electrical engineering or a related field.
• 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows.
• Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.
• Exceptional knowledge of layout design methods, techniques, and methodologies.
• Experience with physical verification tools, such as Calibre or Assura.
• Understanding of semiconductor process technologies and their impact on layout design.

Who You Are:

We are seeking someone with excellent problem-solving and systematic skills, who can work effectively in a team-oriented environment. Familiarity with the Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) is essential. Good communication and interpersonal skills are a must. Experience in writing RTL Code, with solid Verilog, PERL, and Python skills, and TCL as an addition, will be highly valuable. Understanding of static timing analysis and synthesis, DFT/ATPG skills, and high-speed communication protocols are added advantages. Previous experience in customer support and/or silicon bring-up will be a plus.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on developing and verifying high-performance silicon chips. Our team collaborates closely with design engineers and application engineers to ensure the successful integration and functionality of our IPs. We are committed to continuous improvement and knowledge sharing, contributing to the overall success of Synopsys and our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.