Who knew designing PLL’s was so complicated?

Well it comes as no surprise to those that use and design them, that PLL’s are a world unto themselves and very complicated indeed. With PLL’s we are talking about analog designs that rely on ring oscillators or LC tanks. They are needed on legacy nodes, like the ones that IoT chips are based on, and they are crucial for high speed advanced node designs like those at 16nm and below. They are especially important on nodes that are typically considered ‘digital’, yet all the challenges of analog design must be addressed on these processes. Indeed, advanced SOC’s often have numerous PLL’s servicing internal clocking needs and those of external IO.

PLL design involves making many trade offs: for instance, is the precision of an LC tank, with a high Q inductor, worth the area required, or can a much smaller ring oscillator deliver the needed performance? Jitter is the key parameter that needs to be controlled in PLL designs. Across the nodes from 180nm to 10nm there is a need for PLL’s that operate at anywhere from below 100 MHz up to the multi GHz range with low jitter. Applications such as SerDes rely on low jitter in PLL’s.

Last week at the 2017 Silicon Valley TSMC Technology Symposium I had a chance to talk to Andrew Cole and Randy Caplan with Silicon Creations. Their bread and butter is designing analog IP that is used widely across a broad range of process nodes. PLL’s are a part of their expertise. With TSMC rolling steadily on toward 7nm – even 5nm was mentioned during the symposium – IP providers such as Silicon Creations need to deliver high performance analog designs on these FinFET nodes. Andrew talked about one of their most popular PLL designs that is in over 100 unique designs and has been taped out at every imaginable node from 180nm to 16nm. Apparently, the run rate for this one PLL on one 28nm process is around one billion instances per year.

They pointed me to a document on their website that details the specific challenges they faced as this design was moved and verified at successively smaller nodes. From 65nm to 10nm there has been nearly a 3.5X relative increase in the peak transition frequency (fT) of the transistors. At 10nm the fT will be in excess of 500GHz. The material on their website goes into some detail about the tradeoffs between 28nm polygate and 28nm high-K metal gate. Nonetheless, 10nm FinFET continues the progression of fT to higher frequencies.

The real question is, how do analog designs scale as lambda decreases? To help answer this Silicon Creations offer up data comparing their relative PLL area from 180nm to 10nm. Refer to the diagram below to see how this has progressed.

While it is not as dramatic as digital area scaling, it is enough to help lower costs. Each smaller node has presented its own challenges to analog designers, much as they have to digital designers. Silicon Creations has dealt with this by developing their own back end design flows. Even though an analog design schematic may look much the same, at FinFET nodes they are now dealing with increasing interconnect resistance, which requires anticipating parasitics earlier in the flow. Also, the quantized nature of W in tri-gate devices leads to changes in transistor parameter specifications.

Silicon Creations covers the gamut when it comes to process node coverage. They are concurrently designing at all the nodes mentioned above – 180nm to 10nm, and have work under way for 7nm. There is more detailed information available, including the material they directed me towards, on their website. It is interesting to see how, on what most people consider to be digital nodes, they sustain delivery of essential building block analog IP for a wide range of designs.