When we talk about open source, free usually comes in the context of “freedom”, not as in “free beer”, and open IP often serves as a base layer of value add for commercialization. The creators of the RISC-V instruction set, now working at startup SiFive, have released specifications for their aptly-named Freedom processor IP cores looking for “enablement of great ideas”.
For those of you who haven’t been exposed to RISC-V yet, the effort traces its lineage to one of the earliest RISC researchers – David Patterson. A team at UC Berkeley including Krste Asanovic, Yunsup Lee, and Andrew Waterman with mentorship and advice from Patterson started a project in 2010 to define a freely-available ISA with lessons learned over nearly three decades of RISC progress. Where most other open ISAs have taken on embedded needs, RISC-V is scalable from embedded to enterprise.
Under leadership of my old friend Rick O’Connor, the RISC-V Foundation is about to hold their 4[SUP]th[/SUP] RISC-V Workshop this week at MIT in Cambridge, MA. Support garnered for RISC-V in just under a year since the Foundation launched is impressive, with names including AMD, Google, Hewlett Packard Enterprise, IBM, Microsoft, NVIDIA, Oracle, Qualcomm, Rambus, and smaller processor IP players including Andes Technology, Codasip, and Cortus.
The challenge for RISC-V is going up against the well-established ARM ecosystem, other processor IP including Synopsys ARC and Cadence Tensilica and Imagination MIPS, and a host of closed microcontroller cores. Many are called, few are chosen. Even with all those choices, the problem I’ve been writing about lately remains: silicon for applications such as the IoT and wearables still is not optimized for the job, using an off-the-shelf part often brings compromises, and starting a new custom chip design remains expensive – especially a server-class chip.
RISC-V has caught fire in academic circles as well, with an open source EDA methodology built around the Chisel design compiler. I had one of the early implementers, John Leidel from the GoblinCore64 project at Texas Tech University, on my panel at #53DAC. There are many other projects, including lowRISC at the University of Cambridge and the SHAKTI project at IIT Madras. Many of these projects are headed for HPC applications, leveraging capability such as the TileLink protocol for cache coherent transactions.
At some point, if RISC-V is to be more than just another open source community with interesting research, somebody has to move to broad-scale commercialization. It is fitting that the principal inventors of RISC-V formed SiFive and are taking a lead role to do just that. SiFive has defined two families of IP cores, one targeting server-class processors and the other deeply embedded parts.
The Freedom U500 series (with U standing for Unleashed – I like that a lot) is the big core, designed on TSMC 28nm targeting 1.6 GHz. With a full MMU it is Linux-ready, and SiFive says they have other peripherals including memory controllers, PCIe 3.0, GigE, and USB 3.0, along with TileLink support for up to 8 cores.
The Freedom E300 series (with E for Everywhere) is the part aimed at microcontroller segments. One interesting wrinkle is the process – it’s on TSMC 180nm, likely a spot TSMC has a lot of capacity for a very low cost. (Freedom, not free wafers. SiFive declined to talk about core IP pricing without an NDA.) Without an MMU, the Freedom E300 does have support for the 16-bit RISC-V Compressed Instructions for better code density.
Platform specifications for both families are being released, with everything needed to create software. The software story for the Freedom E300 is particularly intriguing. SiFive says they have a FreeRTOS port, but waiting in the wings is another OS: Apache MyNewt, yet another open source IoT entrant gaining momentum.
Hardware development kits in the form of three different FPGA platforms are also available. For the Freedom U500 core IP, there is a very inexpensive Arty FPGA Dev Kit with a Xilinx Artix-7 FPGA mostly for software development, and a more capable VC707 FPGA Dev Kit with a Xilinx Virtex-7 for full high-speed interface development. For the Freedom E300 core IP, there is the SF2+ FPGA Dev Kit featuring the Microsemi M2S010 SoC and an Arduino shield interface on the baseboard.
More details on the processor core IP including the Freedom platform guides and links to the dev kits are available on the SiFive web site.
Will SiFive succeed? Embedded markets take a lot of patience. Hearkening back to the early days of ARM, they were a small team with 12 people when spun off from Acorn, they shifted focus from workstations to embedded, and they targeted makers of things like hard drives and audio add-in cards – way before they showed up in a mobile phone. They spent a huge amount of effort on developing AMBA to make it easy to integrate the core IP, and debug tools, and foundry relationships.
Taking a look at the 4[SUP]th[/SUP] RISC-V Workshop Agenda, we see what’s taking shape in the ecosystem. For example, I can tell you privately from other conversations that RISC-V is being looked at in SSD circles very carefully, both because of the processor core itself potentially replacing ARM in SSD controllers, and as a more creative approach to building big data analytics platforms where an open, configurable SSD controller handles pre-processing tasks in something like Apache Spark.
I don’t expect the small team at SiFive will be a huge threat to ARM overnight (thank goodness, no proclamations of “ARM killer” nonsense from anyone, see M*CORE in the pages of “Mobile Unleashed”), but I look at the open source processor IP community that is developing and it is a compelling model, much more so than single-vendor processor IP efforts out there. We look forward to hearing about SiFive design wins in the near future, and congrats to them and the RISC-V Foundation and its members for getting to this point.Share this post via: