Starting a career in static timing analysis domain, and now actively working on an opensource implementation flow of RISC-V architecture, has been a journey. For last couple of months, I guess from around March this year, I was hooked to RISC-V buzz which was all over my Linkedin, my messages.
Being an STA and Physical design engineer, it was very important for me to connect RISC-V specification to its implementation on chip. Before that, a good break-up of the topic was needed, and with a bit of research, I found the soul of RISC-V ISA – the Application Binary Interface, popularly called as ABI. You get this one right, and I guarantee, RISC-V will be all yours
ABI (application binary interface), as the name says, is an interface, that helps programs access system hardware and services. Let’s break it down
When users look forward to buying computers, they are, more likely, interested in the appearance and functionality of the computer, whether it serves their purpose. And, very unlikely, user will be interested in its physical design implementation of the chips inside the computer, like whether its high-performance or low power implementation
Now, here, the appearance and functionality, are an example of interface between users and computers. Let’s consider another kind of interface – more VLSI and technical
Application program interacts with standard libraries using an interface called ‘application programming interface (API)’. The very basic example, you must have seen, is while writing a C program where you use ‘#include stdio.h’ – this interface defines the core input and output functions
Next interface is the operating system, which handles IO operations, allocates memory and some other low-level system functions. This layer is, by the way, also the one which converts the function programs into its assembly language program and/or machine language program, providing “bit-patterns” to the underlying hardware. This interface is the ISA interface (in this blog, its RISC-V ISA).
Then, the other VLSI level interface is RTL which implements the RISC-V specifications and is an important interface between the ISA and its physical design implementation
In above image, if you move from right (Hardware) to Left (application program), and then coming from left, if you stop at middle (RISC-V ISA), that’s when you start thinking about this architecture from all angles, like sta, drc, congestion, clock skew, io latency, static and dynamic power, IR and many more.
Coming back to ABI or application binary interface, it consists of 2 parts as shown in above image – one is the set of all user instructions itself, and second is the system call interface through the operating system layer. How does it do that in reality? …..Through registers shown in below image
RISC-V architecture has 32 registers (we explained, in detail, why this architecture has 32 registers in our online course). Application programmer, can access each of these 32 registers through its ABI name, for example, you need know the value of stack pointer or move the stack pointer, all you need to do is “addi sp, sp, -16”, where ‘sp’ is the ABI name of stack pointer.
This blog should give a good head-start towards understanding ABI. Now, once you get the functioning of all ABI names in table shown in above image, believe me, RISC-V is all yours. We have done that in our online course, explaining each and every ABI using an example. You finish the examples, and you conquer the battle.
“When in doubt, just take the next small step”. One step that you can take today, and get closer to this architecture is through the below online course on RISC-V ISA:
TAKE THE FIRST STEP NOW…
I will see you in class and happy learning…
Also Read: Other RISC-V ArticlesShare this post via: