2020 Symposia on VLSI Technology and Circuits

2020 Symposia on VLSI Technology and Circuits
by Admin on 06-16-2020 at 12:00 am

VLSI 2020 is going virtual!

Given the global health concerns associated with COVID-19 (Coronavirus), the organization of VLSI 2020 has decided to hold the 2020 VLSI Symposia on Technology and Circuits as a virtual conference. Although we will not be meeting in Honolulu this year and it will be impossible to reproduce the lively

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Tracing Technology’s Evolution with Patents

Tracing Technology’s Evolution with Patents
by Arabinda Das on 04-23-2020 at 10:00 am

Figure 1

We live in an age of abundant information. There is a tremendous exchange of ideas crisscrossing the world enabling new innovative type of products to pop up daily. Therefore, in this era there is a greater need to understand competitive intelligence. Corporate companies today are interested in what other competitors are brewing… Read More


Webinar: VLSI Design Methodology Development (new text)

Webinar: VLSI Design Methodology Development (new text)
by Tom Dillinger on 08-28-2019 at 10:00 am

Daniel Nenni was gracious enough to encourage me to conduct a brief webinar describing a new reference text, recently published by Prentice-Hall, part of the Semiwiki Webinar Series.

VLSI DESIGN Methodology Development Webiner Replay

Background

I was motivated to write the text to provide college students with a broad background… Read More


What Fairchild, AMD, Actel and Jurassic Park Have in Common

What Fairchild, AMD, Actel and Jurassic Park Have in Common
by John East on 08-26-2019 at 6:00 am

Me.

In the early stories of this series  (Weeks three though six), I talked about what I believe were the three seminal events in the history of the semiconductor:  Shockley’s invention of the transistor, Noyce’s invention of the integrated circuit, and Intel’s 1971 —  the introductions  of the first commercially successful… Read More


Is there anything in VLSI layout other than “pushing polygons”? (4)

Is there anything in VLSI layout other than “pushing polygons”? (4)
by Dan Clein on 12-19-2017 at 12:00 pm

The year is now 1991 and in search for a more peaceful life we decided to move to Canada. At that time, very few companies had advanced flows in VLSI but Ottawa having BNR, Northern Telecom, Mitel, etc., looked to be the most promising place. After a few hiccups in finding a job, I landed in MOSAID, a small company with35 people at that … Read More


Application binary interface, get this right and RISC-V is all yours

Application binary interface, get this right and RISC-V is all yours
by kunalpghosh on 12-15-2017 at 7:00 am

Starting a career in static timing analysis domain, and now actively working on an opensource implementation flow of RISC-V architecture, has been a journey. For last couple of months, I guess from around March this year, I was hooked to RISC-V buzz which was all over my Linkedin, my messages.

Being an STA and Physical design engineer,… Read More


Is there anything in VLSI layout other than “pushing polygons”?

Is there anything in VLSI layout other than “pushing polygons”?
by Dan Clein on 09-12-2017 at 12:00 pm

As I travel a lot in the last 15 years and visited customers as well as friends I was many times invited to talk to the Layout teams. The main purpose is always to encourage automation. So I developed a presentation related to market trend, technology trends, and latest tools advancements. In many cases I present updates from DAC (Design… Read More


The Importance of Transistor-Level Verification

The Importance of Transistor-Level Verification
by Students@olemiss.edu on 04-10-2016 at 7:00 am

According to the IEEE Std 1012-2012, verification is the acknowledgement that a product is in satisfactory condition by meeting a set of rigorous criteria. [3] Transistor-level verification involves the use of custom libraries and design models to achieve ultimate performance, low power, or layout density. [2] Prediction… Read More


Intel is Selling Itself Short on Trigate!

Intel is Selling Itself Short on Trigate!
by Ed McKernan on 05-17-2012 at 9:15 pm

Perhaps the most pertinent comment raised by an analyst at Intel’s Investor Forum last week came from Dan Hutcheson of VLSI Research to Brian Krzanich, the COO and head of global manufacturing and supply chain. He said: “I think you sold yourself short on Trigate, the benefit of fully depleted vs. planar and the impact on leakage.”… Read More