Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register behavior and more. Not that this is trivial; UVM is still a complex animal requiring a lot of training and learning on the job. There continue to be debates about features and extensions: what should be standardized and what should be left to vendor solutions for example. Evolution naturally, but along a fairly clear path.

REGISTER HERE for the Webinar, on January 31[SUP]st[/SUP] at 10am Pacific

The same claim couldn’t be made for SoC and subsystem-level verification, at least until relatively recently. You’re still going to build testbenches using the UVM standard, but a bunch of what UVM offers for block-level verification is less useful at the system-level; for example, constrained-random is a hopeless approach to effective system-level testing. There are other important areas to optimize also, among which getting to a working testbench is the most obvious barrier to starting system-level verification.

At the SoC level, testbenches are much more than a stimulus/monitor/cover shell around a DUT: configuring the design, swapping IPs for VIPs with their transactors, assertions and covers for protocol verification (across the many protocols common in an SoC), along with adding hooks for validating against verification plans, adding performance testing, stress testing and coherency testing. When you consider also that many of these IP come from different sources, with different verification assets, assembling these testbenches is a complex and time-consuming task, often taking days to weeks to get to first effective verification.

But it doesn’t have to be that way. Synopsys’ VC AutoTestbench can assemble an SoC testbench in hours. This will import the DUT description, select and configure VIP, instantiate and connect these within the DUT and build out the test environment. They have this down to a pretty simple 5 step process. DUT and VIPs are read in and configured as IP-XACT, clock, reset and ad-hoc signals can be configured automatically and a testbench drops out. None of this requires protocol expertise or even UVM expertise. You’re up, simulating, and debugging in Verdi in hours rather than weeks. That sounds like a real-time saver.

REGISTER HERE for the Webinar, on January 31[SUP]st[/SUP] at 10am Pacific

Webinar Abstract
Today’s highly complex SoCs typically include multiple embedded processors, a memory subsystem, several interfaces to standard and custom protocols and a sophisticated interconnect architecture. These designs come together from IPs to subsystems to the full SoC, with system-level verification typically done late in the project cycle. Current verification environments don’t scale well from the IP- to SoC-level, are effort-intensive and time-consuming to build, and inherently error-prone. Due to time-to-market pressures, system-level verification to functionally verify the numerous system configurations is often insufficient and incomplete. Hence, there is a pressing need for automation in SoC verification, starting from testbench generation and bring-up.
In this Synopsys webinar, we will discuss how to reduce the time-to-first-test from weeks to hours by automating the process of testbench generation with Synopsys VC AutoTestbench. We will also include a demo of this flow using a real-world design and Synopsys AMBA VIP. Specifically, you will learn:

• How to quickly and easily generate a complete SystemVerilog/UVM verification environment
• How to efficiently reuse SoC-level testbenches for IP & interconnect verification
• How to bring-up the auto-generated testbench and run tests from the Synopsys AMBA VIP test suites

Speakers:

Vaishnav Gorur
Product Marketing Manager – Verification Group
Synopsys

Vaishnav Gorur is currently Staff Product Marketing Manager for Debug & SoC Verification Automation products in the Verification Group at Synopsys. He has over 12 years of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and an M.B.A. from University of California, Berkeley.

Satyapriya Archarya
Senior Manager – Applications Engineering – Verification Group
Synopsys

Satyapriya Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols with several key customers. He has been involved in the development, verification and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. He has over 15 years on experience in design and verification.