Tag: auto-generation

Webinar: Auto-generation of Verification Infrastructure for IP to SoC

Webinar: Auto-generation of Verification Infrastructure for IP to SoC
by Admin on 11-15-2023 at 3:44 pm

DVClub Europe Meeting –November 2023

Agenda (BST):

12.00 GMT – Welcome and Introduction

Mike Bartley,Tessolve

12.00 GMT – Saving Development Time by Automating Verification infra from specifications

Anupam Bakshi, Agnisys

12.30 GMT – Generation of Functional Coverage for RISC-V Processor Verification

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Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am
Categories: Arm, EDA, Synopsys

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register… Read More