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ARM and Mentor Team Up on Test

ARM and Mentor Team Up on Test
by Daniel Payne on 06-27-2011 at 2:31 pm

Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe processor group.

Test Overview

ARM partnership – processor division and physical IP division (Artisan), work with both divisions.
– Main competitor in test is Virage/Synopsys IP
– ARM doesn’t want to partner with Synopsys any more

Tessent – best products from Mentor and LogicVision combined now
BIST (Serdes, PLL, Memory) tools at ITC 2009
– Pre-tapeout for test generation
– Post-tapeout for analysis
Boundary scan, memory bist, pll bist, compression/atpg, logic bist, serdes bist (Biggest competitor is still SNPS)o EDAC numbers: 58% of DFT, 42% in Atrenta, Cadence, SNPS
o ATPG, MENT at 48%
o BIST, MENT at 98%

– Research inanalog bist, stay tuned. Analog fault simulation. Converter BIST – consulting now.
– Defective Parts Per Million (DPPM < 1,000 for consumer, and <10 automotive)
– Hierarchical test approach to work with design methodology
– Multi-core approach (broadcast test patterns to identical cores)
– Test electronics produces a signature
– Yield Analysis – bring up new silicon using a laptop to connect with USB cables to JTAG, tell what the Jitter is on a Serdes using a laptop (both design and test engineers)
– Test & Diagnosis (Layout Aware Diagnosis – failed data from scan and atpg results, netlist, layout, pinpoint the type of defect (via open, shorts, localized), where is my defect?
– Test and Yield Insight – (Best Product of the Year at EDN), announced 18 months agoo Look at all defects across many dies and wafers (volume), with statistical approach it can find systemic defects and type of defects found
o Working with Calibre group to find hot-spot failures (to be announced)

ARM – performance is critical yet how to make it testable?
– New interface to ARM cores, place BIST outside of the processor to keep performance high
– All future arm cores have this new interface
– Pipelined but direct method to the internal core memories (rest of the core is scanned logic)
– (what about working with MIPS ? could be)
– A5, A9 and A15 use this new approach (Cortex) – Shared Bus Support (Mentor term)
– (TSMC reference flow – Tessent)
– Physical IP (Artisan – abandoned internal BIST, now use Tessent BIST at 40nm and below)
– On chip testing and repair of Memories is supported
– Shared customers:

When Synopsys acquired Virage it changed how ARM wanted to partner with Mentor Graphics. The addition of LogicVision BIST tools into the Mentor Tessent family creates a full-service set of test approaches for both Digital and Mixed-Signal SOC designs.


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