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How to Gain Low-Power at High-Performance

How to Gain Low-Power at High-Performance
by Pawan Fangaria on 11-28-2015 at 12:00 pm

In a world of smart devices, high performance is required in order to address several specific needs such as intelligent and immediate data processing for IoT applications, instant response from mobile devices, highly interactive user interfaces, and so on. Most of these devices are battery operated and hence require lower power consumption. Designers are challenged with lowering power consumption in devices without impacting their performance.

There are several techniques, already evolved and still evolving to reduce SoC power consumption by various means such as technology trade-off, hardware design, software design, and using automated tools to measure, analyze and optimize power. However, to get the best out of all these methods a designer or software developer needs to know what to do when and where during the SoC development.

I am pleased to see a detailed presentation in ARM TechConon low-power MCU (Microcontroller) design by Dung Dang, an expert in ultra-low-power architecture and application software design from Texas Instruments. Dung provided actual tips which can be used while developing low-power hardware and software designs.

The MCU vendors typically choose an optimal process node which can provide lowest energy consumption out of leakage and active currents at the best possible operating frequency for the device. Then there is voltage threshold, V[SUB]th[/SUB] for transistors which plays a very important role in trade-off between performance and power. Advanced MCUs use a combination of transistors with different threshold voltages; standard SV[SUB]th[/SUB] for active peripherals and high HV[SUB]th[/SUB] (that exhibits lowest performance and power) for standby logic.

To reduce the overall active power, the power rail can be split into multiple voltage levels. The rail at higher voltage, Vcc can feed the circuit that requires high voltage such as I/O and analog. The lower voltage, Vcore rail can feed core CPU and digital logic.

There is a choice of voltage regulators to generate Vcore. The Low-dropout linear regulator (LDO) is simple to design, cost effective with smaller footprint, and robust; the generated rail is relatively noise-free. The DC/DC converter has ~60% power saving compared to LDO and has higher efficiency (75 – 90%) for moderate to high loads. However, the DC/DC converter has higher noise.

There are also some other design improvements which can be done in the SoCs to reduce power consumption.

The active duty-cycle can be minimized for faster CPU speed, and standby power can be reduced through several techniques such as lower leakage process technology, cell optimization, power gating of idle circuit, turning off idle memory banks, and so on. Low-power UART, I2C, Timer, etc. can be used for low-power peripheral system. The peripherals can be divided into power domains and high-power, high-frequency domains can be gated off during standby. Also, separate power domains can be designed for HV[SUB]th[/SUB] and SV[SUB]th[/SUB]; HV[SUB]th[/SUB] can be used for low-speed peripherals and SV[SUB]th[/SUB] for high-speed peripherals. Only HV[SUB]th[/SUB] gates can be enabled during standby.

To minimize active power one can employ special frequency mode in MCUs and use low-current output power sources. Hardware accelerators can be employed for compute intensive functions such as Advance Encryption System (AES) or CRC, FPU, and DSP engines. Use of DMA can also reduce power consumption.

While there are ample opportunities to reduce power in hardware, there are many techniques that can be applied at the code level in software to reduce power. Highly optimized software can be developed on ARMCortex[SUP]®[/SUP]-M series of processors that can have smaller binaries to fit in smaller devices, consume lesser power and run faster.

It’s important to review the ARM processor architecture to know what is available to leverage on to reduce power consumption. For example, floating point operations should be avoided if FPU is not available on the MCU; unaligned data access should be avoided. On the other hand, the architecture should be utilized to the maximum extent, e.g. use as large variables as the native architecture permits.

For efficient embedded software, special care should be taken in the code, for example using bitmask instead of bit-field; using DMA for repetitive transfer instead of ‘for loop’ or ‘memcpy ()’; terminating unused I/Os; using compiler to build tight loops fitting in MCU cache or buffer.

There are efficient ‘C’ coding techniques on ARM processors available from ARM and elsewhere; a detailed guideline can be found HERE.

Also, there are vendors providing optimized libraries for specific MCUs. These libraries are pre-built with all kinds of optimizations taken into account with specific compiler settings. Some MCUs have built-in ROM libraries that are faster and consume lesser energy compared to Flash or even cache memories. Depending on the amount of task and ROI involved one can decide which way to proceed.

The developers can also use various tools to measure, analyze, and debug various parameters in order to optimize power. Texas Instruments provides ULP Advisor, a code analysis tool that can help developers spotting code inefficiencies. EnergyTrace++[SUP]TM[/SUP] is an efficient energy measurement and debugging system for microcontrollers that can track current, CPU and peripheral states, and identify power black holes.

The MCU developers have a great opportunity to leverage process technology, hardware and software design, and tools to develop low-power and high-performance MCUs, a critical need for today’s electronic systems.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com


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