- Simulate bus traffic, video display and video RAM
- Determine throughput
- Measure latency
- Verify that bus priorities were working
- Optimize the bus interconnect
That was in the 1980’s, however today the SoC architect has the same challenges while using newer prototyping languages and approaches.
When a new SoC is being designed the architect selects the CPU cores, GPU, memory controller, IP blocks, etc. Initially we don’t know the actual interconnect traffic or how each block will share the bandwidth. An EDA company called Carbon Designhas created tools to help you design and optimize your system with SoC Designer. With this tool you can visualize the performance between CPU cores and main memory by plotting out memory bandwidth and latency:
With a virtual prototype and this type of analysis you can design your interconnect to meet the specs and provide adequate QoS (Quality of Service) at the earliest phase of architectural exploration. Select the interconnect models from the Carbon IP Exchange, use AXI traffic generators, and add the memory sub-system models:
Prototyping with IP Blocks
The traffic generators eventually get replaced with your actual IP blocks, like an Aerteris FlexNoC as you finalize an SoC:
At this point you can profile the actual traffic, debug your hardware and software, and analyze cache coherency.
If your system uses a dual ARM Cortex-A15 with coherent ARM CCI-400 interconnect, then you can model this with a reference platform provided by Carbon, called a CPAK:
All of the ACE traffic workloads can be visualized and the hardware coherency profiled:
Virtual prototyping is an accepted approach to designing and optimizing interconnect on an SoC. You could use any language to write your virtual prototype, however you can save a lot of time and effort by using models and tools from Carbon Design.
- Interconnect Optimization, blog by Eric Sondhi
- Interconnect Optimization with SoC Designer, White Paper