Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/the-cost-penalty-why-auto-chips-are-still-in-shortage.17104/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021270
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

The cost penalty: Why auto chips are still in shortage

benb

Active member
Some models for the semiconductor industry include the Competitive Strategy model of Michael Porter, which finds companies can succeed by innovation, by selling at the lowest cost, or both. Another model is the Christiansen Innovator’s Dilemma model which notes that industries may be characterized by steady or disruptive innovation, and by low cost creating or expanding the market. Another modeler is Malcolm Penn who posits a basic driver for semiconductor businesses is the increase in transistors in products which grows at 8% per year on average.

According to BCG, in 2021 demand for auto chips was 118 while supply was 106 in relative terms. In 2022 supply is better at 113 but demand is 121-123. In 2023, BCG predicts, demand will be 124-127 and supply 123. So the shortage persists today, and will continue to persist, but narrow in 2023.
61440BF5-9A0E-4366-A85C-EF093E356FC4.jpeg

The crippling auto chip shortages have yet to be explained fully by the models I’m aware of. So that makes it very interesting from an intellectual and practical standpoint.

The BCG report contains a concept that potentially explains the shortages in mature nodes MEMS and analog; the “cost penalty.”

”The tight supply for analog and microelectromechanical systems chips will likely persist, in part due to the comparative cost penalty of new versus fully depreciated fabrication plants acting as a headwind to new investment.”

I like the BCG cost penalty concept as it is simple explanation for why we still have shortages. No one, not the auto makers, nor their suppliers, is willing to bear the cost penalty, since it would be a poor strategic move. The higher cost supplier would eventually go out of business. So, essentially, low cost is an unassailable moat that prevents new, higher cost capacity for analog and MEMS. This is predicted by the Porter model.

This shifts the debate, in my opinion, from who is to blame (no one is to blame) to what is missing from the market. It seems what is missing is competition; new entrants to the market bringing new capacity with new capabilities that justify the cost increase.

Is this the correct explanation? There have been no new competitors in the MEMS and analog market since the shortage started. That indicates it’s potentially correct. Then why are their no new entrants? Product shortage should incent competition; why not with analog and MEMS?

I think there are special problems with mature markets that require capital investment. It isn’t sexy. The potential upside is limited, while the costs, and the risks, are substantial. So no one wants to go there.

The mature analog and MEMS players also provide a warning to new entrants. They illustrate a market you want to avoid: Low prices, no pricing power, low ROI.

The fact that the mature analog and MEMS players continue operating with such bad conditions may perhaps be the crux of the issue. Until some of them go out of business, the low ROI will scare off new players. So the market has to get worse, to get better.

One of the problems I’ve observed over the years in the semiconductor industry is this industry cyclicality produces deep troughs in profitability. An illustration: During 2008, at Qimonda, the DRAM price fell and Qimonda’s cash cost at the fab I was employed at was $2 more per chip than the market price. We joked about each chip coming with 2 $1 bills attached. That negative ROI wasn’t sustainable and we eventually went bankrupt.

If prices had risen slightly, we might have remained in business in the hope that our ROI would turn positive eventually. I think this is where the mature MEMS and analog fabs are at currently. They are too unprofitable to survive but remain alive for now, perhaps surviving on low cost debt financing, which prevents new entrants and a healthy market.

Higher interest rates may put the zombie MEMS and analog players out of business. Or perhaps new entrants are needed first, to double tap the weak zombies. It will be interesting to see if the cost penalty model is correct, whether zombie companies can survive higher interest rates, and whether the aging Intel, Samsung or TSMC fabs can match the costs of the zombie MEMS and analog players.
 

nghanayem

Well-known member
Thanks for the excellent write up benb! How far can analog devices scale? Is it worth considering if these higher prices push auto companies upmarket to analog devices on 28-45nm nodes? This would harm all of those hundreds/thousands of nm folks and likely force them to shift capacity to mems or bankruptcy. It seems like it would be easier to invest in these newer trailing edge nodes while the mems buissness can spread to the older fabs that would be going underutilized.
 

cliff

Active member
Nghayahem.... YES, and even to 16-12nm. I expect pushback my former neanderthal colleges, but I am going to say it. I have transitioned to being a cannibal intent on pushing analog stick-in-the-muds into retirement. Analog/Mixed-signal automation has arrived on double patterned finfet technology. Yes Ben, there are people pretending to be zombies.

Analog devices work just fine at 28nm and 16-12nm. The architecture must change. Rather than working on a voltage domain, you design in the time domain. Rather than making devices larger to reduce mismatch (Pelgrom's law), you add digital calibration or error correction. The most accurate analog can be made in digital processes without having to push the diffusion out to another zip code. My concern is more about the number of I/O pads you need for size of the chip you are making.

When you talk about costs, there is NRE, costs per die, price per package. Let's start with NRE. A senior circuit designer will be a one-stop-shop. No CAD groups. No layout people. Semi-automation will improved the quality of the design by removing the middle-man. You will see this sooner than you think.

As far as the cost per die/package, designs should no longer be done on the SOC level. They should be done on the SIP level, on an interposer.

For MEMs, can they be put onto or into the silicon interposer, such as Skyworks?
 

jms_embedded

Active member
I think there are special problems with mature markets that require capital investment. It isn’t sexy. The potential upside is limited, while the costs, and the risks, are substantial. So no one wants to go there.

The mature analog and MEMS players also provide a warning to new entrants. They illustrate a market you want to avoid: Low prices, no pricing power, low ROI.

The fact that the mature analog and MEMS players continue operating with such bad conditions may perhaps be the crux of the issue. Until some of them go out of business, the low ROI will scare off new players. So the market has to get worse, to get better.
Excuse me? Have you looked at the gross/net margins of Texas Instruments (TXN) and Analog Devices (ADI) lately? Both are heavy sources of analog ICs. ADI benefits from the high-end products of the two companies it acquired recently, Linear Technology and Maxim Integrated, both fabless manufacturers of specialized & differentiated analog chips. (At my former employer, we would go out of our way to avoid Linear and Maxim ICs because they were often expensive and had long lead times --- but we weren't a large company, and I guess Linear and Maxim hit the right niche with customers who needed to buy the expensive unobtainium to make their systems work better.)

I strongly feel the "cost penalty" thesis is correct --- at least, in its assessment of where we are at present, where 40-90nm nodes on 300mm, and 130nm - higher on 200mm, are "underincentivized" to add new capacity because that would have to pay the price of depreciation, but existing capacity got where it is, because at the time it was brand spanking new and could command a price premium. So new capacity can't compete economically with existing capacity. (There are a few nuances to this argument, but that's the basics... I'm polishing up an article for my blog that covers some of these topics on the chip shortage.)

That doesn't mean the existing manufacturers in this market space are unprofitable. Far from it. It's not like the DRAM situation in the late '90s and early 2000s, where the different manufacturers had to endure through the bloodbath of market downturns in order to survive with a net profit over the semiconductor cycle. DRAM is a commodity, and Elpida and Qimonda weren't able to keep their heads above water to compete with Samsung/SK Hynix/Micron. The analog IC vendors do sell commodity chips --- you can buy TL431s and LM358s from a bunch of different sources --- but each of them has a bunch of differentiated stuff that keeps them successful.

I don't know much at all about MEMS so I'll leave that one for someone else to argue. On the analog side: new, small fabless players are presumably out there, although I haven't looked around much, and now is probably a sucky time to try to get capacity at the foundries. As far as building new fabs to cover the demand on these nodes... if things stay bad, someone will take the risk to do it, but it does have a huge cost penalty. (TI already has.)
 

benb

Active member
Cliff, would you agree if I characterized you as 1) Planning to enter the analog market 2) With 300mm wafers supplied by a foundry 3) With a different technology than incumbent 4) At a higher cost 5) and it replaces the incumbent in an existing application.
 

nghanayem

Well-known member
Excuse me? Have you looked at the gross/net margins of Texas Instruments (TXN) and Analog Devices (ADI) lately? Both are heavy sources of analog ICs. ADI benefits from the high-end products of the two companies it acquired recently, Linear Technology and Maxim Integrated, both fabless manufacturers of specialized & differentiated analog chips. (At my former employer, we would go out of our way to avoid Linear and Maxim ICs because they were often expensive and had long lead times --- but we weren't a large company, and I guess Linear and Maxim hit the right niche with customers who needed to buy the expensive unobtainium to make their systems work better.)
TI has the advantage of being an IDM. I assume benb was mostly referring to fabless folks like skywater who can barely keep their head above water.

From what I’ve heard the mems industry has margins that are too low to justify investment in further capacity or design tools to speed up/automate design. Don’t know how much truth there is with this statement though.

Other than that thanks for your insight. Analog and trailing edge are not my forte; and it is fascinating to learn more about these crucial fields.
 

cliff

Active member
"1) Planning to enter the analog market"
I would say we intend to help the 1-5 man electronic companies develop a high performance chip. These chips have analog and digital (mixed signal). We have both analog and digital (place and route) automation. They need both.
"2) With 300mm wafers supplied by a foundry"
I suppose, if you are saying that 300nm = 28nm and below.
"3) With a different technology than incumbent"
Same as (2)
"4) At a higher cost"
This is a loaded question. Way lower NRE (fewer employees). As far as die costs, an integrated system is cheaper than a radio shack system, but you are on track here. I am not interested in dealing with penny pinching bean counters. Off with their heads!
"5) and it replaces the incumbent in an existing application"
It is disruptive. It replaces tools, existing methodologies, and people. The existing VXL system is like a typewriter and white-out. Careful on your edits. You don't want to lose those 1000s of routes that you created.

As I see it...

180-130: JMS_embedded probably in the power electronics area that can get away with metal4 being the highest routeable layer. We have no interest in that area. JMS is probably not affected by parasitics (EM, yes, RC no) and can throw his designs over the ocean to the cheapest labor area. His processes are more likely to be 130nm and above.

90nm - 40nm is probably useful for huge I/O pad needs, photonics, and acting as interposers. I expect push back on this, but the car industry needs to move on. I agree with TSMC and Mr Gun-slinger here.

28nm. No way as good as finfet/patterned/routable_contact processes, but this process can be laid out manually, I suppose. 16nm layouts take 3x longer. TSMC says no to 40g (my previous favorite) and move to 28, so you gotta do it (apologies to UMC). Note, my company automates this process, but fugeddaboudit...

The IFS announcement on 16nm changed everything. The TSMC 16-12 price dropped (I cannot say more).
We are an EDA company focused on high performance mixed signal and low NRE (senior designer as a one-stop-shop), preferring to semiautomatically migrate/create finfet ASICs. Yes, we handle cheapskate processes too, but the advantage of our tools is that the parasitics are available immediately, so we like high performance circuits. We do not believe the layout designer should be involved in the process. I am not a bigot. Some of my best friends are layout people ;-), but their days are over (I expect another angry phone call from a guy who wrote the pink/purple book one of these days). Schematics should be updated in a layout friendly manner (bit slicing, pulling out the big caps and resistors to the next higher level, etc).

We are interested lowering NRE to convince gadget guys to move from FPGAs and boards to ASICs and interposers. Saving pennies... not interested. I was at a big company in silicon valley that was interested in squeezing down the area of their wireless designs and missed the market to companies getting out the door quickly. Penny wise, dollar foolish. They lost due to the stupidity.

As far as power and speed, interposers with direct high speed connections rather than power hungry CML to PC boards. The industry is changing so quickly right now, it seems that whatever chips are out in the market now will be obsolete in 2 years. The technology advances, especially in 2.5D packaging, is changing everything. These are exciting times to be in this sector.

EUV is currently too pricey for ASICs
 

benb

Active member
Cliff, what you’re working on sounds so novel and interesting.

Is there an overall term for what you’re describing, or is it too new to have a name?
 

jms_embedded

Active member
180-130: JMS_embedded probably in the power electronics area that can get away with metal4 being the highest routeable layer. We have no interest in that area. JMS is probably not affected by parasitics (EM, yes, RC no) and can throw his designs over the ocean to the cheapest labor area. His processes are more likely to be 130nm and above.
LOL, I am enjoying this characterization. I don't do chip design. :) As for my employer, well...

It's all about economics, disruptive technology will always change the playing field once it enters serious competition, and even the dinosaurs have to play the game if they don't want to die. But sometimes the question is which game to play. (Or how to play it.)

Cliff, what you’re working on sounds so novel and interesting.
I'll second that. Somewhere on YouTube is an Alvin Loke presentation about circuit design in the FinFET era, and he had hinted about analog. He was at Qualcomm but is now at NXP, which should tell you something.
 
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cliff

Active member
We are just providing the EDA tools (front to back), tunable analog IP (serdes, PLLs, etc) that can be torn apart and pieced together differently, and the ASIC layout services.

Our digital P&R is not novel. It is the same as what was done 30 years ago. We call it the "It's so easy, an analog designer could do it" GUI.

On the analog side, it is also not novel. We just automated the same things that the analog designer would do manually. Migrate, optimize, compact, route, EM, RCx, reoptimize, update, compact, route, etc. We just do it automatically.
We call it Mr. Herkelbogerstein's whizbang EDA environment with cross probing at all times and correct by construction layouts. We may come up with a shorter name in the future.
 

cliff

Active member
JMS (can I call you Mr. Tandy?), I didn't want to call your company a dinosaur... well, actually I used to, but you guys have made some good purchases and have hired some good IC designers that I know, so you guys may have advanced to the late 1990s. I knew your employer well in 2010. We did a few circuits for them, but the meetings were always bad. One of their directors told me that he didn't care about time to market and stormed out of the meeting. In another meeting, I was asked not to offend layout designers, but I didn't agree to that and Layout Guy stormed out. I don't think I am allowed to enter the building anymore. Hopefully they have progressed. I haven't changed my views.
 
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Paul2

Active member
Some models for the semiconductor industry include the Competitive Strategy model of Michael Porter, which finds companies can succeed by innovation, by selling at the lowest cost, or both. Another model is the Christiansen Innovator’s Dilemma model which notes that industries may be characterized by steady or disruptive innovation, and by low cost creating or expanding the market. Another modeler is Malcolm Penn who posits a basic driver for semiconductor businesses is the increase in transistors in products which grows at 8% per year on average.

According to BCG, in 2021 demand for auto chips was 118 while supply was 106 in relative terms. In 2022 supply is better at 113 but demand is 121-123. In 2023, BCG predicts, demand will be 124-127 and supply 123. So the shortage persists today, and will continue to persist, but narrow in 2023.
View attachment 968
The crippling auto chip shortages have yet to be explained fully by the models I’m aware of. So that makes it very interesting from an intellectual and practical standpoint.

The BCG report contains a concept that potentially explains the shortages in mature nodes MEMS and analog; the “cost penalty.”

”The tight supply for analog and microelectromechanical systems chips will likely persist, in part due to the comparative cost penalty of new versus fully depreciated fabrication plants acting as a headwind to new investment.”

I like the BCG cost penalty concept as it is simple explanation for why we still have shortages. No one, not the auto makers, nor their suppliers, is willing to bear the cost penalty, since it would be a poor strategic move. The higher cost supplier would eventually go out of business. So, essentially, low cost is an unassailable moat that prevents new, higher cost capacity for analog and MEMS. This is predicted by the Porter model.

This shifts the debate, in my opinion, from who is to blame (no one is to blame) to what is missing from the market. It seems what is missing is competition; new entrants to the market bringing new capacity with new capabilities that justify the cost increase.

Is this the correct explanation? There have been no new competitors in the MEMS and analog market since the shortage started. That indicates it’s potentially correct. Then why are their no new entrants? Product shortage should incent competition; why not with analog and MEMS?

I think there are special problems with mature markets that require capital investment. It isn’t sexy. The potential upside is limited, while the costs, and the risks, are substantial. So no one wants to go there.

The mature analog and MEMS players also provide a warning to new entrants. They illustrate a market you want to avoid: Low prices, no pricing power, low ROI.

The fact that the mature analog and MEMS players continue operating with such bad conditions may perhaps be the crux of the issue. Until some of them go out of business, the low ROI will scare off new players. So the market has to get worse, to get better.

One of the problems I’ve observed over the years in the semiconductor industry is this industry cyclicality produces deep troughs in profitability. An illustration: During 2008, at Qimonda, the DRAM price fell and Qimonda’s cash cost at the fab I was employed at was $2 more per chip than the market price. We joked about each chip coming with 2 $1 bills attached. That negative ROI wasn’t sustainable and we eventually went bankrupt.

If prices had risen slightly, we might have remained in business in the hope that our ROI would turn positive eventually. I think this is where the mature MEMS and analog fabs are at currently. They are too unprofitable to survive but remain alive for now, perhaps surviving on low cost debt financing, which prevents new entrants and a healthy market.

Higher interest rates may put the zombie MEMS and analog players out of business. Or perhaps new entrants are needed first, to double tap the weak zombies. It will be interesting to see if the cost penalty model is correct, whether zombie companies can survive higher interest rates, and whether the aging Intel, Samsung or TSMC fabs can match the costs of the zombie MEMS and analog players.

The shortage is mainly 200mm. Most of them are captive clients who can't switch to 300mm, or too low volume (and car chips are low volume.)

There are no new 200mm equipment being made, and there will not be any more new 200mm capacity on the market.

MEMS, and Analog are made on 200mm because of their low volumes, or lack of 300mm process for particular product.

200mm fabs are more profitable now than they were at the time of their start now.

The second capacity contention is on 40nm to 65nm gap. This is where everyone who could move to 300mm, but not able to chase the node shrink race stayed.

The NREs of proprietary sub 40nm nodes are still huge, and for FINFET nodes, they grow exponentially. 40nm is also the last node on which you can switch fabs more or less painlessly.

MCUs will not go below 40nm in their majority because they don't benefit much from extra performance, and their dies are too tiny anyways. The benefit for automotive ASICs is even smaller. The chip in BOSCH power steering is 300 micron for example because it just a few thousand gates.
 

Paul2

Active member
Chipmakers are also not orienting solely on developed markets. They know that economic cycle usually hits 3rd world countries much harder than the West, and they are usually are who consume the most of mature node output.

India's car industry for example is a giant consumer of legacy automotive ICs because auto makers like to sell their 15-10 years old models in part kits for local assembly.
 

jms_embedded

Active member
There are no new 200mm equipment being made, and there will not be any more new 200mm capacity on the market.
that's interesting...

In an article in SemiEngineering, SEMI reported 32 new fabs constructed from 2016 - 2022. Most are SiC or MEMS or China.

Also from SemiEngineering: (in 2020)

Lam continues to manufacture deposition, etch, cleaning tools and other products for 200mm fabs. Some deposition and photoresist strip systems were introduced to the market as 300mm-only solutions. “We have since released 200mm versions to provide our customers with enhanced technical performance and productivity at 200mm,” Haynes said.
 

Paul2

Active member
Deposition tools are not steppers. They basically only needed to change the port size, and put in a wafer grabber (effector) sized for 200mm. Things are different for more sophisticated tools. As I know, there is no ALD tool for 200mm as such, so 200mm will not get 300mm deposition processes, and will stay with CVD.

Maybe more 200mm tools will arrive, but they will be made for making power electronics on 3-5, not CMOS logic.
 
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cliff

Active member
Great points Paul. That's what I thought when we automated 65nm and 40nm, but then the foundry gods exclaimed "Act like engineers, Suck it up, and move on!"

I love 40g, but not if TSMC isn't going to let us MPW it. Circuit designers should embrace the ability expand their horizons with new architectures, have more metal layers, less voltage droop (leakage), embed an FPGA, and add more memory and calibration.

The way I see it, 180/130nm, 16nm, HBM, interposer. With the competition at 16nm, I don't see 90-22nm (Rad Hard + redundancy vs lead package is another topic). Your turn...

Note: Denso is helping to fund 16nm in Japan.
 

Paul2

Active member
Great points Paul. That's what I thought when we automated 65nm and 40nm, but then the foundry gods exclaimed "Act like engineers, Suck it up, and move on!"

I love 40g, but not if TSMC isn't going to let us MPW it. Circuit designers should embrace the ability expand their horizons with new architectures, have more metal layers, less voltage droop (leakage), embed an FPGA, and add more memory and calibration.

The way I see it, 180/130nm, 16nm, HBM, interposer. With the competition at 16nm, I don't see 90-22nm (Rad Hard + redundancy vs lead package is another topic). Your turn...

Note: Denso is helping to fund 16nm in Japan.

TSMC obviously wants to nudge more clients to more expensive nodes by creating these inconveniences, and they remove the risk of you going to another foundry without physical redesign if you leave 40nm.

I bet they will stay 40, or even do a process refresh, but only for a few chosen big clients they know they can lose.

With NREs, and design cost on <40nm being so huge, it's really unwise of them to wish 40/65 nm consumers do a self-harming move.

To most of F500, or basically any semi company whose name you hear on a TV, <40nm design cost is a pocket change, and they will go for it.

But for the low margin no-name ASIC, and MCU markets, which make the lion share of the IC volume, it's absolutely not a pocket change, nor would they be able to pull a <40nm redesign with their own (very cheap) engineers.
 

cliff

Active member
TSMC "removes the risk of you going to another foundry without physical redesign if you leave 40nm." How?

"I bet they will stay 40, or even do a process refresh, but only for a few chosen big clients they know they can lose." You are probably correct. The little guys getting access to the TSMC 40 MPW is unlikely. The metal stack on GF/On/Sky is ridiculous.

Low profit margin companies.. Fire your salesman (Note: I don't have a salesman)

Not able to create "<40nm redesign with their own (very cheap) engineers".... Ouch!!! Did you hear that Mr. Tandy? Is Mr. Paul correct? Defend your guys!
 

Paul2

Active member
TSMC "removes the risk of you going to another foundry without physical redesign if you leave 40nm." How?

All <40nm fab service on the market uses double patterning, which is all proprietary process, and fab specific.
 
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