imec study of EUV stochastic defects in wafer yield at SPIE 2024

[Fred Chen]

https://spie.org/advanced-lithography/presentation/Study-of-EUV-stochastic-defect-on-wafer-yield/12954-4#_=_

As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do not account for the stochastic-driven defects that changes by both pitches and critical dimensions (CD) in EUV lithography. In this study, a novel approach that incorporates EUV stochastics into the yield modeling, using calibrated stochastic defects from wafer data is introduced. Then a comparative analysis of yield for various EUV insertion scenarios is meticulously performed. Additionally, strategies to enhance yield in EUV lithography, including CD retargeting are proposed.

 

[Tanj]

using calibrated stochastic defects from wafer data is introduced.

It was a good conference.

The calibrated data will be key, and it is not clear that IMEC will have access to the real world data. Many presentations discussed smoothing technologies that use chemical and physical properties of the mask resist to smooth LER in steps between litho and etch. These included developer chemistry and optimal use, transfer layers, DSA, directional etch, even some new things like electron flood were hinted. So, what you see in exposure stochastics is not what the mask resist pattern eventually looks like when the chip surface etch happens.

 

[hskuo]

It was a good conference.

The calibrated data will be key, and it is not clear that IMEC will have access to the real world data. Many presentations discussed smoothing technologies that use chemical and physical properties of the mask to smooth LER in steps between litho and etch. These included developer chemistry and optimal use, transfer layers, DSA, directional etch, even some new things like electron flood were hinted. So, what you see in exposure stochastics is not what the mask eventually looks like when the chip surface etch happens.

SPIE Advanced Lithography is a very good conference and imec has an advanced R&D line which works very well in pathfinding studies. I would say the yield model in the real world (real products) could be more complex and deviated from this model, but the methodology is similar. Here in imec's work, it was based on stochastic defects in simple line/space patterns which might not meet real world practice which including device window/design rule/process variation checking in 1D/2D patterns, overlay stacking, process integration and also random defects for each processes and calibrated by real defect inspection, etest and EOL yield data. The edge roughness from mask could be a concern, but due to features in mask is 4x larger than on wafer and scanner is a low pass filter for edge roughness, the roughness propagation from mask to wafer could be still not critical.

 

[Fred Chen]

Resist edge roughness was known before EUV, there had been work on smoothing it as soon as ArF arrived. The dose variations make it worse, but the techniques can still be used, and now there are more available as has been shown at SPIE. The smoothed edge can still move around, though, this is the EPE that still needs to be addressed. As far as the defects themselves are concerned, generally there are the missing-resist and excess-resist types; these are minimized at some optimum CD (~half-pitch). But the rates can be so low that massive (i.e., slow) e-beam sampling would be needed to catch them - not sure if companies are taking the time for the full evaluation.

 

[hskuo]

Resist edge roughness was known before EUV, there had been work on smoothing it as soon as ArF arrived. The dose variations make it worse, but the techniques can still be used, and now there are more available as has been shown at SPIE. The smoothed edge can still move around, though, this is the EPE that still needs to be addressed. As far as the defects themselves are concerned, generally there are the missing-resist and excess-resist types; these are minimized at some optimum CD (~half-pitch). But the rates can be so low that massive (i.e., slow) e-beam sampling would be needed to catch them - not sure if companies are taking the time for the full evaluation.

Fred: If you are talking about stochastic effects and the fail rate is about 1~1/10 ppb level, it will be very very challenging to catch them in-time (1-2 hours) using current sampling methodology upon this random events. KLA had estimated that we needed 1000x inspection throughput improvement or 1000x beams or columns. There are many ways using in DFM to mitigate the impacts, but we still need statistically reasonable sampling to predict the failure. Precise metrology should be crucial for this prediction. There are lots of smart people work on it now.

 

[Fred Chen]

Just read this paper, it turns out they are calibrating to previous papers' assumptions of defect density, but the trends they got were as expected.