Daniel Payne
Moderator
In EDA we love three letter acronyms so CPS joins our growing list, and as I visit DesignCon this week I read more and more about CPS. In the past EDA vendors would offer analysis tools to distinct categories of users, like: Chip Designers, Package Designers, System Designers. The presumption was that you could just divide up the design disciplines and expect that when you integrated your chip into a package, and the package into the chip, that the system would just work OK.
Well, those days are behind us because there is clearly an electrical interaction between these three design abstractions that must be analyzed in order to produce a system that works.
I talked last week with Dian Yang, Ph.D. at Apache Design Automation to learn about Chip Power Models (CPM) and why the modeling is important to analyzing CPS. At the system level I need to analyze for:
With such a CPM you can use a SPICE circuit simulator to run analysis that is Static, Dynamic (you supply vectors) or Dynamic with automated vectors.
The concept of a CPM has been around for at least 5 years, now Apache is taking it to the next level of accuracy by adding several new capabilities:
Q: Could I simulate an entire PC motherboard?
A: Yes, you can simulate this for power nets.
Q: Is there a library for CPM models?
A: Too early in time, although the IDMs can create their own libraries.
Q: How do I create CPM models?
A: Use the RedHawk tool to create a CPM model.
Q: Interoperability?
A: CPM is a SPICE netlist (Berkeley SPICE format will work with: Cadence, Mentor, Synopsys, Mentor simulators) of the power network.
Q: What about maximum Size?
A: You can simulate the whole board as long as you have a CPM model for each chip. Component companies may provide a CPM model.
Q: Any IP issues with a CPM?
A: Not really, it’s a SPICE netlist of power nets, not the active devices. System companies like this approach.
A: This also allows co-analysis of Chip+Package+System.
A: IDM uses this flow to create CPM and let Systems designers build demo boards with confidence.
Q: What is in CPM?
A: Just the PDN, switching power, multi-die for TSV devices.
Q:Uses for CPM?
A: A system designer can do: PDN analysis, EMI, Thermal.
Q: What types of Thermal analysis?
A: Die, package, board.
Q: Comparison to Gradient?
A: They only do die-level analysis, not package and board. May not get correct boundary conditions for the die.
Q: Do you model K (mutual inductance)?
A: No, because it's just too small, impractical, 100 to 1000 times smaller than L.
Q: How do you chose input stimulus?
A: It’s up to user (VectorLess or VCD).
Q: How do I know which vectors to run for my Chip to get the worst case power?
A: We have experience that is documented per type of chip design to help you use RedHawk to use best practices to create CPM models.
Q: How do I use CPM?
A: Early, in-design or sign-off. Three times you can benefit from analysis. First use was sign-off only, now during design they can reduce costs by careful analysis of noise. How many layers in my PCB? How many pins for VDD/VSS.
Q: Mode dependent? (Audio, video, standby modes?)
A: One model for all modes.
View attachment 321
Q: On-die LDO inclusion?
A: Voltage source or regulator is outside of the chip. 110AC input, 1.5V output. Low Drop Out chip is inside of new consumer chips. Multiple power domains (1.1, 1.09, 1.08, 1.07) would use too many input pins, inside chip use LDO to create multiple power domains.
Q: Probing of internal nodes?
A: Now supported for internal nodes.
Q: Variable power models?
A: Start a chip in standby mode, then go to active mode. You can see that power varies based on mode of device.
View attachment 322
Q: Do I need your SPICE tool?
A: Users can run their own Spice and waveform viewer to get analysis results, or they can run Sentinel and get analysis results.
A: All Apache tools are MT and multi-core ready.
Q: Where do I learn more about using CPM 2.0?
A: At DesignCon we have a CPS User Group and workshop.
Well, those days are behind us because there is clearly an electrical interaction between these three design abstractions that must be analyzed in order to produce a system that works.
I talked last week with Dian Yang, Ph.D. at Apache Design Automation to learn about Chip Power Models (CPM) and why the modeling is important to analyzing CPS. At the system level I need to analyze for:
- Power Integrity
- Timing
- EMI
- Thermal
With such a CPM you can use a SPICE circuit simulator to run analysis that is Static, Dynamic (you supply vectors) or Dynamic with automated vectors.
The concept of a CPM has been around for at least 5 years, now Apache is taking it to the next level of accuracy by adding several new capabilities:
- Mode dependent (it knows the different operating modes of your chip)
- Resonance aware (depending on the mode and frequency you see different current waveforms)
- Variable power (the modes have different power levels)
- Chips with Low Drop Out (LDO) regulators can now be simulated
- Internal nodes can now be probed for voltage or current
Q: Could I simulate an entire PC motherboard?
A: Yes, you can simulate this for power nets.
Q: Is there a library for CPM models?
A: Too early in time, although the IDMs can create their own libraries.
Q: How do I create CPM models?
A: Use the RedHawk tool to create a CPM model.
Q: Interoperability?
A: CPM is a SPICE netlist (Berkeley SPICE format will work with: Cadence, Mentor, Synopsys, Mentor simulators) of the power network.
Q: What about maximum Size?
A: You can simulate the whole board as long as you have a CPM model for each chip. Component companies may provide a CPM model.
Q: Any IP issues with a CPM?
A: Not really, it’s a SPICE netlist of power nets, not the active devices. System companies like this approach.
A: This also allows co-analysis of Chip+Package+System.
A: IDM uses this flow to create CPM and let Systems designers build demo boards with confidence.
Q: What is in CPM?
A: Just the PDN, switching power, multi-die for TSV devices.
Q:Uses for CPM?
A: A system designer can do: PDN analysis, EMI, Thermal.
Q: What types of Thermal analysis?
A: Die, package, board.
Q: Comparison to Gradient?
A: They only do die-level analysis, not package and board. May not get correct boundary conditions for the die.
Q: Do you model K (mutual inductance)?
A: No, because it's just too small, impractical, 100 to 1000 times smaller than L.
Q: How do you chose input stimulus?
A: It’s up to user (VectorLess or VCD).
Q: How do I know which vectors to run for my Chip to get the worst case power?
A: We have experience that is documented per type of chip design to help you use RedHawk to use best practices to create CPM models.
Q: How do I use CPM?
A: Early, in-design or sign-off. Three times you can benefit from analysis. First use was sign-off only, now during design they can reduce costs by careful analysis of noise. How many layers in my PCB? How many pins for VDD/VSS.
Q: Mode dependent? (Audio, video, standby modes?)
A: One model for all modes.
View attachment 321
Q: On-die LDO inclusion?
A: Voltage source or regulator is outside of the chip. 110AC input, 1.5V output. Low Drop Out chip is inside of new consumer chips. Multiple power domains (1.1, 1.09, 1.08, 1.07) would use too many input pins, inside chip use LDO to create multiple power domains.
Q: Probing of internal nodes?
A: Now supported for internal nodes.
Q: Variable power models?
A: Start a chip in standby mode, then go to active mode. You can see that power varies based on mode of device.
View attachment 322
Q: Do I need your SPICE tool?
A: Users can run their own Spice and waveform viewer to get analysis results, or they can run Sentinel and get analysis results.
A: All Apache tools are MT and multi-core ready.
Q: Where do I learn more about using CPM 2.0?
A: At DesignCon we have a CPS User Group and workshop.
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