Gainesville, FL – January 11, 2024 – The advance program is available for the 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative. DVCon U.S. will be held March 4-7 at the DoubleTree by Hilton Hotel in San Jose, California.
“DVCon continues to be the must-attend conference for the practicing design and verification engineer,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair. “Now in its 36th year, DVCon offers attendees presentations addressing day-to-day challenges, real experiences, and solutions, as well as a peek into what’s on the horizon. DVCon also provides many networking opportunities during the exhibition and coffee breaks to give participants time to engage with colleagues and experts in the industry to learn about new technologies and standards.
“The Steering Committee has worked hard to put together a wide-ranging program of technical presentations that offer something for everyone,” Fitzpatrick continued. “Our tutorials and workshops on Monday and Thursday will cover many important topics from Portable Stimulus, Functional Safety, RISC-V design and verification, and Low-power verification to Network-on-Chip optimization, Clock/Reset Domain Crossing and Static Signoff, Large Language Model code generation and Chiplets. The main technical sessions on Tuesday and Wednesday will feature 42 paper presentations on everything from Coverage, Formal and Mixed-Signal design and verification to Verification Planning and Regression Management, UVM and SystemVerilog verification techniques and Artificial Intelligence and Machine Learning. We’ll also have over 20 posters on an even wider array of topics. The Poster Ninja Warrior session returns this year and will include four posters battling it out for top honors on Wednesday March 6. Each Poster Warrior will be given five minutes to present their poster, followed by an insightful Q&A from a panel of expert judges. Audience reaction is encouraged and is an integral part of the judging process, creating a dynamic and interactive event.
“In addition to the technical sessions, Tuesday afternoon will feature a Keynote presentation from Paul Cunningham, Senior VP/GM at Cadence, and a special guest. Wednesday will kick off with a great panel discussion on ‘When Will We Be Able to Say, “EDA-GPT, Verify My ASIC”?’, and we’re adding a second Keynote presentation on Wednesday afternoon as well, featuring Alex Starr, AMD Corporate Fellow. These sessions are included in the free exhibits-only registration package, so I hope everyone will attend,” concluded Fitzpatrick.
Registration is open. Registration for the keynote, panel, guest speaker and exhibits-only is free.
For the latest updates regarding the conference and expo, please visit the website.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.
For more information, please contact:
Laura LeBlanc
Conference Catalysts, LLC
352-872-5544 Ext. 115
lleblanc@conferencecatalysts.com
Barbara Benjamin
HighPointe Communications
503-209-2323
barbara@hipcom.com
“DVCon continues to be the must-attend conference for the practicing design and verification engineer,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair. “Now in its 36th year, DVCon offers attendees presentations addressing day-to-day challenges, real experiences, and solutions, as well as a peek into what’s on the horizon. DVCon also provides many networking opportunities during the exhibition and coffee breaks to give participants time to engage with colleagues and experts in the industry to learn about new technologies and standards.
“The Steering Committee has worked hard to put together a wide-ranging program of technical presentations that offer something for everyone,” Fitzpatrick continued. “Our tutorials and workshops on Monday and Thursday will cover many important topics from Portable Stimulus, Functional Safety, RISC-V design and verification, and Low-power verification to Network-on-Chip optimization, Clock/Reset Domain Crossing and Static Signoff, Large Language Model code generation and Chiplets. The main technical sessions on Tuesday and Wednesday will feature 42 paper presentations on everything from Coverage, Formal and Mixed-Signal design and verification to Verification Planning and Regression Management, UVM and SystemVerilog verification techniques and Artificial Intelligence and Machine Learning. We’ll also have over 20 posters on an even wider array of topics. The Poster Ninja Warrior session returns this year and will include four posters battling it out for top honors on Wednesday March 6. Each Poster Warrior will be given five minutes to present their poster, followed by an insightful Q&A from a panel of expert judges. Audience reaction is encouraged and is an integral part of the judging process, creating a dynamic and interactive event.
“In addition to the technical sessions, Tuesday afternoon will feature a Keynote presentation from Paul Cunningham, Senior VP/GM at Cadence, and a special guest. Wednesday will kick off with a great panel discussion on ‘When Will We Be Able to Say, “EDA-GPT, Verify My ASIC”?’, and we’re adding a second Keynote presentation on Wednesday afternoon as well, featuring Alex Starr, AMD Corporate Fellow. These sessions are included in the free exhibits-only registration package, so I hope everyone will attend,” concluded Fitzpatrick.
Registration is open. Registration for the keynote, panel, guest speaker and exhibits-only is free.
For the latest updates regarding the conference and expo, please visit the website.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.
For more information, please contact:
Laura LeBlanc
Conference Catalysts, LLC
352-872-5544 Ext. 115
lleblanc@conferencecatalysts.com
Barbara Benjamin
HighPointe Communications
503-209-2323
barbara@hipcom.com