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Already in use. More would be nice but if it was easy they already would. Shrinking the dimensions does not make such materials easier.
I wonder if such diverse-circuit tactics will help much for AI chips where mostly they are grinding out low precision tensors and moving data.
Sounds like...
Really challenging to try tricks like negative capacitance ferroelectrics or tunnelling combined with the complex fabrication of ribbon or CFET. These complex shrinks reward conservative devices. Whether the construction is ever mastered well enough to start adding gate trickery - maybe, but...
K change makes no difference, since gate capacitance is set by need to control the field in the gate. The point of high-K was to increase thickness to avoid tunneling while applying the same field to the gate.
GAA shortens the gate, which is nice for CPP reduction, but it adds a 4th side so C...
Yes, and AI computation is already at the thermal limit with close to ideal layouts. It can gain a bit from functional diversity with denser logic (separate pipelines for int8, FP8, BF16, etc.) but as more of the modelling is simply learning to use the fastest units - FP4/Int8 which are...
Figure around $30 per W for average of GPUs and other machines plus infrastructure and Capex to provide the power. So, around 3 to 4GW indicated.
The most interesting way to get that might be a strategic location with good local solar and wind plus a serious investment in grid upgrades for...
This is the Oct 2023 release referred to in the Reuters presser:
https://www.bis.doc.gov/index.php/about-bis/newsroom/2082
It updates a rule from a year prior which is linked towards the end of the update.
OneAPI, CUDA, and ROCM are intermediate levels. PyTorch and TensorFlow are modelling languages (though TF has its own modelling layer when compiling to TPUs, it uses CUDA or ROCM as intermediates too). No-one builds models in intermediate languages anymore, though they do import...
There are two situations, chiplet is at the end of a spoke, or chiplet is in the middle of a fabric. At the end of a spoke the bandwidth is in proportion to the chiplet. In or out, the BW depends on the resources on that chip. Generally smaller chip, smaller interconnect needed, same...
Not very big. This paper from Nvidia probably describes the pre-production version of their chip to chip fabric Phy: https://ieeexplore.ieee.org/document/10011563
I think your first remark - Nvidia have already mastered large dies - combined with the maturity of N4 explains why they stick with...
Win mostly for TSMC with a deepening grip on package and test, which must have been leverage SKH hoped to do more with. Short term for SKH, long term for TSMC.
75% return of money on home-run profits is WAY cheaper than investor money. The only issues should be how much red tape is also involved, otherwise that counts as easy money.
Perhaps 7/6 is judged to bifucate either to interest in low cost 8LPP or 8LPU, while n5/4 process is capturing more perf or density oriented projects, and n7/6 fab capacity is being refurbished to match?
If it were me, I would switch to something like UCIe for beachfront density better match to their fabric, and put the heavy serdes on outboard chiplets. That would considerably reduce their memory bottleneck on large models.
Their architecture penalizes them for circuit space on IO wasted at...
Clearance price. Apple no longer offers it, base is M2 at $999 and new M3 starts at 1099. And getting a reasonable memory size is at breathtaking price - $200 per 8GB, even more expensive than HBM3e.
Seems little risk Microsoft will struggle to compete on price. Apple, as usual, is expensive.
And what they foresee. This is an often overlooked key benefit. All the futures funnel through TSMC at the moment. Any one customer may stumble, but the ones who see the correct path will grow, and TSMC has all paths covered.
I use the processes. The people with the jobs of making the processes might want to think about the feedback.
Great that you think energy per operation is obvious - so you would agree that numbers showing actual progress would be useful, right?
No one publishes them today, no press or analyst...
Ah, but what is "performance"? Look at SRAM, which stalled around the 7nm level. The ideal cell layout was a known factor and none of the tricks used since then to make smaller logic have been much help for SRAM. It can help shrink array periphery and the rest of the chip, some benefit, but...
