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Hi Cliff,
Thanks for the interest. I have 2 Berkeley EECS CS kids. Son, Kyle Kranen, works for NVIDIA in the machine learning research group. I can’t speak for him, but I think he’s having the time of his life right now in the generative and LLM AI whirlwind.
His team just put together the models and associated backend for the NVIDIA AI Playground, a place to try different generative LLM models using NVIDIA data centers and software.
Daughter CS grad, Kayla, has her dream job doing software and data engineering at Riot Games in LA. (She‘s a big time gamer)
OpenTitan and in-memory computing sound important and interesting, but not sure it falls into either one’s highest interest zones. I can introduce you to either, with a little more background, but I’m guessing they are low odds right now. Both are on Linked In if you want more info.
It sounds like they have a lot of opportunities. My company goes by the name of Analog Rails, but we are about to DBA Western Semiconductor. We compete with Cadence.
Hi Cliff, I knew a little bit about Analog Rails back in my Synopsys days. I guess you are leveraging your EDA design technology into actual chips ? I’ve heard a little about compute-in-memory tech from Micron and their FWDNXT technology, but I think they have spun that out into a new company.
Correct, but for customers chips (ASICs) In the past we only automated analog, but more recently we have created the entire tools suite, which includes digital place and route, DRC, and LVS. With the completion of the tool suite, we decided to design ASICs for customers. We stopped advertising since 2014 and went to hiding. We are finally going to launch in November. What did you do at Synopsys?
I ran a corporate marketing and program management team that worked with semiconductor and IP partners bringing up an optimizing new technologies. One of the folks on my team was responsible for bringing up analog PDKs across multiples foundries using the PyCells / OpenPDK strategy, until the Laker acquisition kind of changed things up, where I learned about you.
Digital P&R to DRC/LVS - You've got a tough row to hoe, even if you have the best and most efficient chip implementation products in the world, especially in DRC/ERC. Foundry qualification is tough.
But I like your approach - going after the ASIC because that sidesteps much of the qualification pain with foundries. But also challenging since the ASIC business is highly differentiated based on the qualified analog / interface IP in your repertoire, a la Broadcom and their lock on of their high speed PHYs).
Our niche is creation, not verification. It is mostly correct by construction. What isn't CBC, we have DRC checkers for... just as long as the user stays "on the rails". If we detect an off grid situation, we ask the user to allow an autofix, else they are on their own.
Thanks for the interest. I have 2 Berkeley EECS CS kids. Son, Kyle Kranen, works for NVIDIA in the machine learning research group. I can’t speak for him, but I think he’s having the time of his life right now in the generative and LLM AI whirlwind.