Every so often we have a discussion about the compactness of a new process. You know, what does it mean to be a 2nm process when nothing is actually 2nm. Suggestions often include things like transistors per sq mm or the size of some key standard logic cells like NAND2, D-FlipFLop, and SRAM in some sort of weighted average.
But there is a whole other set of dimensions rarely discussed and almost never disclosed:
- Ceff, the effective capacitance of a transistor for the purpose of switching states
- Cw, the average capacitance per micron of wires in the metal layer
- microns of wire average per CMOS pair in some standard circuit like an int8 multiply-accumulate (routing efficiency)
- Vdd, the minimum useful voltage for doing something like running an int8 MAC at 2GHz.
Why are these interesting? Because switching energy, C V^2 / 2, is the limit to efficiency and density in many applications of concern, and if you know these values you can calculate the average switching energy of a CMOS pair in a given process.
Which applications are concerned about this? Oh, little things like AI GPUs, where the arithmetic is crowded to the density limit and operating at 50% per clock switching rate on arithmetic gates and 200% on clock gates/drivers, leading to heat limited density rather than lithography limited density. You can easily exceed 100W/cm2 at a 1.5GHz clock rate with a process as dense as Intel 4 - that exceeds the power density of an H100.
If a CFET can be 4x denser but does not meaningfully improve the capacitance and voltage, then reaching the same clock rate will require as yet unproven technology to remove the intense heat from the chips. Besides which, it does nothing to allow AI be more efficient in terms of delivering functionality per Joule, so it will not help clouds become more environmentally friendly.
Perhaps the relentless march of process density is soon to reach its "Pentium 5" moment of roadmap to irrelevance, where the goal of increased density no longer is the right goal for major markets. We should be looking at energy intensity of switching for some of the most economically valuable markets.
But there is a whole other set of dimensions rarely discussed and almost never disclosed:
- Ceff, the effective capacitance of a transistor for the purpose of switching states
- Cw, the average capacitance per micron of wires in the metal layer
- microns of wire average per CMOS pair in some standard circuit like an int8 multiply-accumulate (routing efficiency)
- Vdd, the minimum useful voltage for doing something like running an int8 MAC at 2GHz.
Why are these interesting? Because switching energy, C V^2 / 2, is the limit to efficiency and density in many applications of concern, and if you know these values you can calculate the average switching energy of a CMOS pair in a given process.
Which applications are concerned about this? Oh, little things like AI GPUs, where the arithmetic is crowded to the density limit and operating at 50% per clock switching rate on arithmetic gates and 200% on clock gates/drivers, leading to heat limited density rather than lithography limited density. You can easily exceed 100W/cm2 at a 1.5GHz clock rate with a process as dense as Intel 4 - that exceeds the power density of an H100.
If a CFET can be 4x denser but does not meaningfully improve the capacitance and voltage, then reaching the same clock rate will require as yet unproven technology to remove the intense heat from the chips. Besides which, it does nothing to allow AI be more efficient in terms of delivering functionality per Joule, so it will not help clouds become more environmentally friendly.
Perhaps the relentless march of process density is soon to reach its "Pentium 5" moment of roadmap to irrelevance, where the goal of increased density no longer is the right goal for major markets. We should be looking at energy intensity of switching for some of the most economically valuable markets.
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