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Recent content by saifmk

  1. S

    5nm wafer cost very high

    Sounds quite reasonable! Makes a lot of sense that there's heterogeneity across the board. FWIW, I want to be clear that our intent was *not* to be sensationalist -- we ran it by some experts before publishing and tried to extremely transparent about our methodology so that anybody can inspect...
  2. S

    5nm wafer cost very high

    I used the latest analysis Handel Jones (IBS) released; see slide 8 here which suggests $100M for 16nm and $542M for 5nm. You're right that his older projection (shown in the chart you pasted) overshot 16nm compared to his newer backward looking estimate. In my mind, the real issue is there is...
  3. S

    5nm wafer cost very high

    Design costs: I used data from IBS (and Gartner which matches up with similar estimates); IBS in particular has been cited by lots of industry folk (including I think SIA) and industry analysts, so I assumed it is at least reasonable. That said, they provide generic costs independent of die size...
  4. S

    5nm wafer cost very high

    I did notice it references GF 7 nm, but was citing it to refer to EUV/DUV compatibility requirements. TSMC's N7+ also uses EUV for some layers and DUV for others (see here). Foundry price doesn't include design costs. Design costs are accounted for separately (see p. 24 and 41). And yes, that...
  5. S

    5nm wafer cost very high

    You might be right that a lot of fab equipment is identical for 10 nm and 7 nm. Still, I think there are at least some cases where new tools are needed. For example, TSMC started using EUV for some layers of its more advanced 7 nm process; and depending on which generation of ASML's EUV tools...
  6. S

    5nm wafer cost very high

    Great point that the same fabs are used for some of these nodes. We didn't take this explicitly into account, and I agree that it would improve the analysis. (I'd also note that we were especially interested in the overall trendline of costs, and accepted some degree of node-to-node error.) That...
  7. S

    5nm wafer cost very high

    Thanks, all, for the discussion! I'm an author on the report. Initially, I'd note that we don’t expect our calculations to produce precise predictions of TSMC wafer prices at each node. Instead, our goal was to produce as good of a methodology as we could based on open-source data -- with the...
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