Webinar: Improving Efficiency and Quality of Verification Environments with Automation

Online

Synopsys Webinar: Tuesday, October 18, 2021 | 10 a.m. Pacific REGISTER HERE Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. …