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Part 1: OSVVM - Leading Edge Verification for the VHDL Community (US) Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair Thursday, May 26, 2022 11:00 AM - 12:00 PM (PDT) Abstract: OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, …
LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series) Part 2: Faster than "Lite" Verification Component Development with OSVVM (US) Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair Thursday, June 9, 2022 11:00 AM - 12:00 PM (PDT) Abstract: Some methodologies (or frameworks) are so complex that …
Abstract: OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional …
