Webinar: Using Formal Datapath Validation to Verify AI Processor Computations hosted by Synopsys

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Summary For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs, AI processors are also datapath heavy …

Webinar: Cloud Enabled Simulation- Ansys Gateway Powered by AWS

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Description Simulation is more accessible than ever, and unlocking its full potential will deliver innovation and results. Are you restricted by CPU or GPU counts? Do you find your team sacrificing quality or speed depending on the project and priorities? How can Ansys Gateway help? Join us as we discuss what our customers are doing …

Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)

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Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …

Webinar: Accelerating Photonic Design with HPC, GPU, and Cloud

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Join our upcoming webinar to see how you can accelerate your photonic innovation by leveraging Lumerical simulations with CPU or GPU on HPC and cloud. Time: September 26, 2023 Venue: Virtual About this Webinar This webinar will showcase our High-Performance Computing (HPC) capabilities for the Lumerical photonic simulation suite, focusing on FDTD. Lumerical FDTD works …

Webinar: Speos GPU Empowers Design Exploration in Interactive Live Preview

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Join Ansys Senior Product Manager Mathieu Reigneau as he discusses the Speos GPU enhancements in the 2023 R2 release that introduces a brand-new explorative workflow using Interactive Live Preview. With Interactive Live Preview, you can navigate and interact with the optical project. Automatically resume the Live Preview with new parameters providing designers with unlimited "what-if …

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)

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Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)

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Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …