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Overview As designs grow in complexity, rigorous formal verification is essential to meet aggressive requirements for power, performance, area, and time to market. Equivalence checking, static verification, automated ECO, and constraint design for clock domain crossing (CDC) are some of the challenges that signoff designers have to consider. Join this quarterly webinar on Cadence® Conformal® …
Synopsys Webinar | Tuesday, August 16, 2022 | 8 a.m. Pacific To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However, during the late-stage functional ECO (engineering change order) phase, the automated ECO tool needs …
