Despite the many challenges we’re all facing, 2020 was a year of growth for Agnisys. We have expanded our user base, introduced new products, and developed unified flows and methodologies to help our users be even more successful. We’re excited to take the next step in our evolution by scheduling our first user group event. We’ve …
Continue reading "AUGER 2021 – Agnisys User Group Educational Roundtable"
Description Automatic generation of System Verilog Assertions for block level register specification, chip-level RTL design aggregating leaf level design, and RTL wrapper connectivity checks at SoC level. Time Apr 28, 2022 10:00 AM in Pacific Time (US and Canada) REGISTER HERE
Description Learn how to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators, bridges, channels, bus fabrics, muxes, etc. wherever needed. REGISTER HERE
Description Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents …
Continue reading "Webinar: Centralized Register Design and Verification from a Golden Specification"
*Company Email is Required for Registration* This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single "executable" specification. Appropriate Audience: ● Architects/RTL Designers ● Verification Engineers ● Pre-Silicon Validation Teams ● Post-Silicon Lab Bring-up Team Members ● Technical Writers ● …
*Please use your work email so we know who the audience is* Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: - Speed and power requirements lead to designs with multiple asynchronous …
