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DVCon San Jose February 27th – March 2nd

DVCon San Jose February 27th – March 2nd
by Bernard Murphy on 02-10-2017 at 7:00 am

DVCon is fast approaching, less than 3 weeks away. As a verification geek, this must be one of my favorite  conferences, so I’ll be there; you’ll see me at tutorials, presentations and wandering around the Exhibit hall. (Pictures here from the 2016 DVCon – many of the same attendees will be at this year’s conference after all :cool:)

As usual, Monday is tutorial day, which I personally find very helpful to stay current with emerging/evolving standards in verification. The day kicks off with a session on creating portable stimulus models in the soon-to-be-finalized portable test and stimulus standard (PSS). Quite a few companies are already using this in various (pre-ratified) forms so I expect it to take off fast. The afternoon continues with a review of the next step in UVM (IEEE 1800.2) and impact this may have on existing verification environments. Finally, you can wrap up with a tutorial on SystemC design and verification – what’s new in the synthesizable subset definition, advice for high-performance modeling and an update on the emerging UVM-System-C standard, so you can reuse your System-C testbenches at RTL.

Tuesday is papers, posters and an intriguing lunch topic (Cadence-sponsored) on whether verification needs differ between edge nodes, hubs, networks and servers. Throughout, all the papers and posters look interesting. I’ll just mention a few that particularly caught my attention: Using UVM sequences to layer protocol verification (Microsoft), Emulation-based low-power validation (Samsung), trends in verification in 2016 (Harry Foster, Mentor), Assertion-based verification for AMS designs (poster, TI), Formal strategies for IP verification (poster, Microsoft), Regression efficiency with Jenkins (poster, Mentor), Optimizing random test using Machine Learning (ARM).

Wednesday starts with a can’t-miss session – users talk back on the portable stimulus standard. Given the  audiences I usually see at DVCon, I expect to hear lively debate. Again, a few topics of special interest for me include: Early software development/verification using hybrid emulation/virtual prototyping (Samsung), Making formal mainstream (Intel), Machine Learning-based PVT/worst-case coverage in AMS (TI). The lunch is sponsored by Synopsys with fellow Atrenta alum Piyush Sancheti moderating a discussion on how industry leaders approach verification using Synopsys technology.

The post-lunch panel could be exciting, depending on how controversial the panelists wants to be, debating what SystemVerilog has done for us (or to us) and what might come after. In afternoon papers, I like: Ironic but effective, how formal can improve your simulation constraints (Mediatek), and Methods to improve verification reuse in AMBA-based designs (SK Hynix).

Thursday is back to tutorials, kicking off with Cadence talking about new approaches to reinventing SoC verification. Mentor have framed a tutorial on formal in an entertaining task – how to verify an FPGA-based solar-powered rescue drone using only formal, when you’re depending on that drone working to get out word that you need to be rescued. Synopsys follows with a very important tutorial on managing low power verification complexity, organized by another fellow Atrenta alum, Kiran Vittal. Low power design has made verification significantly more complex. How do you know you have covered all realistic possibilities, given a seemingly boundless range of configuration and switching options and how can you systematically approach power verification?

Mentor hosts a lunch on trends in verification with a view to an Enterprise Verification platform – should be interesting. Afternoon tutorials start with Cadence talking about IP verification and warning this is not a solved problem. They’ll discuss how to optimize coverage across the spectrum of verification techniques. Mentor follows with a tutorial on how to create a complex UVM testbench in a couple of hours. I’m curious to see how they do that. Synopsys closes with a tutorial on optimizing productivity with formal and getting to closure with formal (a perennially intriguing topic).

If you are involved in verification, DVCon is the one conference each year you cannot afford to miss. Signup HERE.

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