SystemC: User Group update from DAC

SystemC: User Group update from DAC
by John Swan on 06-05-2014 at 12:00 pm

I always enjoy attending the SystemC User group to see what is being done by users of SystemC. This time was no exception. Not only is it FREE, but the professional networking around the meeting, presentations, and break times are terrific.

There were 5 paper presentations at the North American SystemC User Group (NASCUG) on Monday, including an Accellera standards update from Shishpal Rawat, Chair of Accellera. NASCUG is collocated at DAC. I am on committee for reviewing the presentations. Thanks goes to David Black, of Doulos, for Chairing this event.

The full agenda is posted at www.nascug.org and the presentations will be made available within a week.

A highlight for me was the keynote paper on UVM in SystemC. This is a new work by Fraunhofer and gaining wider support within Europe, was done primarily to allow UVM to be extended to the system level. UVM in SystemVerilog is viewed as a block level verification solution. This work has been contributed to Accellera which plans a vote this fall on establishing it as the UVM standard for SystemC.

The UVM in SystemC has not yet been benchmarked against UVM in SystemVerilog. Up to now they have been focusing on making the implementation fully compatible with the existing UVM standard. Would you like to give it a try?

Additionally, Intel is working on Out-of-Order parallel simulation in SystemC in order to take better advantage of the multicore processors available today while keeping with the sc_thread and sc_method without change. As you can imagine, this takes a more intelligent compiler that can smartly look for data dependencies at a higher level of granularity. However, when unknowns such as pointers are used, it reverts to not using OoO execution for that. Standard parallel execution can give a speedup of 14x running on 2 Intel® Xeon X5650 CPUs with 6×2 cores each. Using Intel’s OoO execution approach this increases to about 80x speedup. Other tests show a greater improvement. Through my activities I am aware that Intel has been at the forefront of advanced design methodologies. Intel is partnered with the Center for Embedded Computer Systems, University of California, Irvine on this effort.


Finally, but important to me, was there were two presentations on High Level Synthesis (HLS) at this NASCUG. I was glad to see more work being done on HLS friendly IP. In this case CircuitSutra has developed an AMBA AXI4 bus that uses HLS. This provides more flexibility and hides the detailed protocol details from the user. Similarly, NEC‘s CyberWorkBench HLS tool suite provides a bus generator, the output of which feeds into their HLS tool. A user simply does a read(x,y) or write(x,y) to the bus without concern for the protocol details. Additionally AdaptIP is focused on developing IP using an HLS flow. I have plans to visit them at the IP community at DAC today. See my blog on the HLS for IP Panel in the DAC Pavilion here.

Please review the NASCUG presentations when you see they are posted (I hope soon) and let me know here what you think. I will post a comment when the presentation slides become available.

lang: en_US


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