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Webinar: Semiconductor Reliability and Product Qualification

August 5 - August 8

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Package reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past, reliability meant discovering, characterizing and modeling failure mechanisms, and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins, and other factors. This requires information on subjects like: statistics, testing, technology, processing, materials science, chemistry, and customer expectations. While customers expect high reliability levels, incorrect testing, calculations, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, qualifying semiconductor components, or supplying tools to the industry.

What Will I Learn By Taking This Class?

Participants will learn to develop the skills to determine what failure mechanisms might occur, and how to test for them, develop models for them, and eliminate them from the product. This skill building series is divided into four segments:

  • Overview of Reliability and Statistics. Participants will learn the fundamentals of statistics, sample sizes, distributions and their parameters.
  • Failure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, thermomechanical effects, interfacial fatigue, and others.
  • Qualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.
  • Test Strategies. Participants will learn about the JEDEC test standards, how to design screening tests, and how to perform burn-in testing effectively.

Course Objectives

  • The course will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
  • Participants will be able to gather data, determine how best to plot the data and make inferences from that data.
  • The course will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
  • The course will offer a variety of video demonstrations of analysis techniques, so the participants can get an understanding of the types of results they might expect to see with their equipment.
  • Participants will be able to identify the steps and create a basic qualification process for semiconductor devices.
  • Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
  • Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

Course Objectives

  1. The course will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
  2. Participants will be able to gather data, determine how best to plot the data and make inferences from that data.
  3. The course will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
  4. The course will offer a variety of video demonstrations of analysis techniques, so the participants can get an understanding of the types of results they might expect to see with their equipment.
  5. Participants will be able to identify the steps and create a basic qualification process for semiconductor devices.
  6. Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
  7. Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

Course Outline

Day 1

  1. Introduction to Reliability
    1. Basic Concepts
    2. Definitions
    3. Historical Information
  2. Statistics and Distributions
    1. Basic Statistics
    2. Distributions (Normal, Lognormal, Exponent, Weibull)
    3. Which Distribution Should I Use?
    4. Acceleration
    5. Number of Failures

Day 2

  1. Overview of Die-Level Failure Mechanisms
    1. Time Dependent Dielectric Breakdown
    2. Hot Carrier Damage
    3. Bias Temperature Instability
    4. Electromigration
    5. Stress Induced Voiding
    6. BEOL Dielectric Reliability
  2. Package Level Mechanisms
    1. Moisture/Corrosion
      1. Failure Mechanisms
      2. Models for Humidity
      3. Tja Considerations
      4. Static and Periodic stresses
      5. Exercises
    2. Thermo-Mechanical Stress
      1. Models
      2. Failure Mechanisms
    3. Chip-Package Interactions
      1. Low-K fracture
    4. Through Silicon Via Reliability
    5. Thermal Degradation/Oxidation

Day 3

  1. Board Level
    1. Package Attach (Solder) Reliability
      1. Creep/Sheer/Strain
      2. Lead-Free Issues
      3. Electromigration/Thermomigration
      4. MSL Testing
    2. Board Level Reliability Mechanisms
      1. Interposer
      2. Substrate
  2. Use Condition Failure Mechanisms
    1. Electrical Overstress/ESD
    2. Radiation Effects
  3. Test Structures and Test Equipment
  4. Developing Screens, Stress Tests, and Life Tests
    1. Burn-In
    2. Life Testing
    3. HAST
    4. JEDEC-based Tests
    5. Exercises

Day 4

  1. Calculating Chip and System Level Reliability
  2. Developing a Qualification Program
    1. Process
    2. Standards-Based Qualification
    3. Knowledge-Based Qualification
    4. MIL-STD Qualification
    5. JEDEC Documents (JESD47H, JESD94, JEP148)
    6. AEC-Q100 Qualification
  3. JEDEC Tests
  4. Exercises and Discussion

Instructional Strategy

By using a combination of instruction by lecture, video, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The handbook offers hundreds of pages of additional reference material the participants can use back at their daily activities.

The Semitracks Analysis Instructional Videos™

One unique feature of this workshop is the video segments used to help train the students. Reliability Analysis is a visual discipline. The ability to identify nuances and subtleties in graphical data is critical to locating and understanding the defect. Some tools output video images that must be interpreted by engineers and scientists. No other course of this type uses this medium to help train the participants. These videos allow the analysts to directly compare material they learn in this course with real analysis work they do in their daily activities.

Instructor Profile

Christopher Henderson, President of Semitracks

Christopher Henderson

Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks Inc., a United States-based company that provides education and semiconductor training to the electronics industry.

From 1988 to 2004, Chris worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia’s Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

At Semitracks, Chris teaches courses on failure and yield analysis, semiconductor reliability, and other aspects of semiconductor technology.

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Details

Start:
August 5
End:
August 8
Event Tags:
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Website:
https://www.semitracks.com/courses/reliability/semiconductor-reliability-and-product-qualification.php

Organizer

Semitracks, Inc.
Phone
505-858-0454
Email
info@semitracks.com
View Organizer Website

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