Webinar: Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis

Date: Thursday, April  25, 2024

Time: 14:00pm (Taipei Time)

Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment can uncover SI/PI issues early in the design process, leading to faster signoff of designs. With analysis shifting left in the design cycle, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks, gigabit-speed serializer/deserializer (SerDes), and the latest double-data rate (DDR) memory interfaces.

In this Webinar, we will discuss how to design serial links (SerDes), DDR memory interface and power supply design, etc., using Sigrity Aurora with Topology explorer, System SI to design Conduct signal/power quality analysis in the different stages, and empowers EEs to create successful products on time and on budget.

Attendees will learn to address: 

• Impedance/Coupling Analysis
• Crosstalk/Reflection Analysis
• IR Drop Analysis

REGISTER HERE