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Webinar: RISC-V system debug & analysis made easy with Lauterbach TRACE32 and Tessent Embedded Analytics
October 8 @ 9:00 AM - 10:00 AM
Processor trace gives software developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. In this presentation, Siemens and Lauterbach will give an overview of how processor trace can be used to improve embedded software and applications. We will explain the RISC-V Efficient Trace (E-trace) specification and cover the capabilities of the combined RISC-V debug and trace solution based on the Tessent Embedded Analytics and TRACE32® debug and trace tools including a demonstration. The presenters will be available for live Q&A at the end of the webinar.
Siemens is a key contributor to the RISC-V Efficient trace specification. Lauterbach is the leading supplier of debug and trace tools for embedded systems and key contributor to the RISC-V debug and trace standards. The presentation will include a demonstration of the combined solution, which shows the efficient and simple debugging and tracing of even heterogeneous, complex RISC-V based chips.
Who should attend:
- SoC Architects
- Software Architects
- Embedded Software Engineers
- Anyone considering or already using RISC-V
What you will learn:
- What the RISC-V Efficient trace (E-trace) standard is and how it reduces some of the risks of adopting RISC-V
- How the non-intrusive visibility that it provides is used to understand program behavior for advanced debugging and code optimization
- How the Tessent Enhanced Trace Encoder is part of a complete SoC debug solution
- How to use Lauterbach’s TRACE32® Debug and Trace tools in order to gain extensive insight into a RISC-V SoC with Tessent Embedded Analytics
Speakers:
M. Sc. Michael Schleinkofer
System Engineer, Lauterbach GmbH
Michael Schleinkofer has been working at Lauterbach as a System Engineer since 2019. In 2020 he became a member of Lauterbach’s RISC-V Debug and Trace team and has a special focus on E-Trace and Siemens’ debug and trace solutions. Additionally, Michael is a regular attendee in RISC-V International’s Debug, Trace and Performance Monitoring Special Interest Group and also contributed to the ‘Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V’ Specification. He studied Computer Science at the OTH Regensburg and graduated in 2019.
Mike Sharp
Product Engineer, Siemens – Tessent Embedded Analytics
Mike Sharp has had a number of technical sales and customer facing roles during his 30 year career in the semiconductor industry. He joined the Tessent Embedded Analytic team in Feb 2019 as Application Engineer providing customers with pre and post sales support. In May 2024 Mike joined the Tessent Embedded Analytic Product Management team providing a wealth of experience in SoC debug, analytics and performance monitoring.
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