EDA Acquisition to Drive SoC realization

A week ago I was reading an article written by Daniel Nenni where he emphasised about semiconductor acquisitions to fuel innovation. We would see that in a larger space, not only in semiconductor and FPGA manufacturing companies (e.g. Intel and Altera) but also in the whole semiconductor ecosystem. If we see it from technical perspective, acquisition will take place whenever there is some value in a company which can produce a larger sum by merging with its acquirer. Although I am not going into financial aspect here, but would like to mention that the financial stress also reduces with the merger of innovative companies.

EDA is an essential enabler of the large size and high complexity SoC realization today. As we see it today, an SoC description has to start from RTL or even from a higher level of abstraction. The design has to converge into the most optimized PPA (Power, Performance and Area) layout in the minimum possible time. So, definitely a large scale innovation is required in EDA space too.

Last week I wrote about an innovative approach taken by Atrenta for designing a lint-clean RTL design that can provide very fast closure of the design. This week, at the start of DAC 2015, we are hearing about this important acquisition in EDA space. Synopsys, the leader in EDA space is acquiring Atrenta, a true RTL implementation, optimization and verification company. Last month, I had written about Synopsys’ ‘Silicon to Software’ solution for semiconductor system design and I see that strategy being implemented quite fast. I have been following Atrenta for some time and I see its SpyGlass platform providing a complete solution at RTL level. In my view, it will complement quite well with Synopsys’ strength in design and verification platform.

Atrenta’s GenSys provides a unique solution for RTL re-structuring for design optimization at RTL stage. And Atrenta’s formal verification technology provides one of the most effective solutions for verification at RTL level. The BugScope provides a very effective ‘Assertion-based Synthesis’ solution. These products can complement quite well with Synopsys’ Verification Continuum and Galaxy Design platforms.

Also, Atrenta’s SpyGlass power, CDC, Physical, constraint management solution, and IP Signoff kit are state-of-the art solutions that work at the RTL level. Clearly this RTL level platform is in the right direction towards ‘Silicon to Software’ strategy of Synopsys.

This combination of technologies will further accelerate the convergence of the overall design towards closure as most of the verification and optimization loops will close at the RTL level. A design re-work loop at the RTL is order of magnitude faster compared to that at gate or layout level. So, this will further boost Synopsys’ ‘Shift Left’ strategy.

Read the press release here for more information.
Also read: “Semiconductor Acquisitions will Fuel Innovation!”
“A Robust Lint Methodology Ensures Faster Design Closure”
“SoC’s Shift Left Needs Software Integrity”

Pawan Kumar Fangaria
Founder & President at www.fangarias.com