Solido Design Automation Update 2012

Having spent a considerable amount of time with Solido, they were one of the founding members of SemiWiki, I can tell you that at 20nm the Variation Designer Platform is a critical part of the emerging 20nm design methodology. You can read more on Solido’s SemiWiki landing page HERE. It is well worth the click.

With technology rapidly going mobile, demand is driving IC development to high-integration, higher-performance at lowest power, a competitive cost, and still in time to meet market demands. In creating these SoCs at the leading edge, process nodes increased variability is a serious risk. Solido is THE leading solution provider to derisk variation, providing maximum yield at the performance edge, with specific solutions for memory, standard cell, low power and analog/RF design.

You can tell a lot about a company by their DAC content. For a relatively small company Solido is delivering a very big value proposition:

Solido Variation Designer Memory+ is used for memory design to achieve maximum yield on high-performance designs. Solido will demonstrate how Memory+ runs the billions of Monte Carlo samples needed for high-sigma (up to 6-sigma) verification of bit cells and sense amps, giving fast and accurate visibility into the increasing effects of variation on design in nanometer technologies. Using the industry-standard simulators commonly used in memory design to achieve SPICE-accurate results, Memory+ is fast enough for use in the design loop. Memory+ will be demonstrated both from the command line and from a graphical environment.

Solido Variation Designer Standard Cell+ delivers the highest-quality standard cell libraries in less time. Solido will demonstrate how Standard Cell+ optimizes a library of cells across the increasingly significant variation effects in nanometer technologies, allowing efficient migration of a standard cell library to a smaller process node or second source. Attendees will see how to leverage Solido’s meta-simulation technology to enhance standard SPICE simulation and manage performance-yield tradeoffs. Operating at the command line for full batch operation, Standard Cell+ is also used as an environment for design debug and results visualization.

Solido Variation Designer Low Power+. To minimize power in today’s portable devices, numerous power states in SoCs need to be considered and verified against thousands of corner cases. Solido will demonstrate how its Low Power+ uses Fast PVT meta-simulation technology, delivering a typical 2x-10x productivity gain in design verification coverage across power states, PVT corners, and layout RC corners. Attendees will see how Low Power+ actively finds and simulates only the worst-case corners while providing predictive results for non-worst-case conditions, giving full coverage at a fraction of the simulation cost.

Solido Variation Designer Analog+. Solido will demonstrate how its Analog+ product builds on the well-established Cadence® Virtuoso® Custom Design Platform to delivers simulation efficiency and design closure against worst-case PVT corners and extracted 3-sigma statistical corners. Analog+ delivers a 10x average efficiency increase for PVT signoff, more consistent Monte Carlo analysis with multiple stop-on-yield criteria, fast extraction of statistical corners at a target sigma, and efficient, intuitive, interactive design sizing. All capabilities provide extensive visualization and debug to assist in efficiently achieving high-yielding designs.

You can sign up for a Solido DAC meeting HERE. Send me a note and I will meet your there!