A (R)evolution in Hardware-based Simulation Acceleration

The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach to managing this resource across an increasingly diverse set of users and verification environments.

I recently spoke with Frank Schirrmeister, Senior Group Director, Product Management, for the Cadence System and Verification Group, who shared his excitement about the capabilities of this new platform.

Simulation Hardware Acceleration as a General-Purpose Resource

Simulation acceleration platforms fall into two categories – processor-based and FPGA-based architectures.

Cadence offers both types of systems – Palladium and Protium – and has been developing flows to enable verification teams to move workloads between the two as seamlessly as possible, to leverage the best of both offerings. (For a discussion of Palladium and Protium migration, please refer to this earlier Semiwiki article: “What’s the Difference Between Emulation and Prototyping?”)

Typically, these platforms are reserved for large, system-level verification workloads, where the throughput of software simulation tools are inadequate for the task. Model compilation and job execution are usually managed by a smaller verification team, who are experts in the nuances of:

• partitioning the model across platform domains (e.g., FPGA’s or acceleration hardware clusters)
• managing multiple, concurrent project workloads running on the platform
• integrating attached in-circuit hardware emulation interface modules
• debugging methods specific to these platforms

The increasing complexity of SoC’s and the IP integrated into these chip designs requires that simulation acceleration no longer be primarily focused on system verification, often used in a narrow interval of time in the overall project development schedule. Rather, IP and SoC verification plans also need to incorporate the benefits of accelerated simulation, in various potential scenarios – more on “usage models” shortly.

Recognizing this need, Cadence approached the development of the Palladium Z1 platform to be more of a general-purpose resource, readily available and familiar to a broader cross-section of the verification team, across the full gamut of IP, Core, SoC, and system environments, as illustrated in the figure below.

First, some of the evolutionary improvements in the Palladium Z1 offering…

Palladium evolution
Leveraging technology scaling has enabled Palladium Z1 to improve specifications significantly over the previous Palladium XP-II platform:

• up to 4X maximum model capacity
• up to 2X performance in model build and resource allocation
• up to 1.5X runtime execution throughput
• 2X power density improvement (watts per million gates)

Extending multiple boxes to accommodate larger models has been enhanced to utilize optical fiber and Infiniband interfaces for the inter-system connectivity. (Existing Palladium-XP users will no doubt acknowledge that multi-system model domain management and cabling has been a pain.)

Cadence has continued to emphasize model portability between platforms, including the Cadence Incisive Enterprise Simulation software toolset. Utilizing a model compilation front-end that is aware of semantic differences between software simulation and acceleration (e.g., multi-state vs. two-state evaluation), verification environments and intermediate runtime results can be moved from IES to Palladium Z1 and back again, using a methodology that Cadence refers to as a “hotswap”.

Debug databases are readily off-loaded from the Palladium Z1, for off-line post-processing.

And, the ability to integrate in-circuit emulation with Palladium is supported. The Emulation Development Kits (EDK) are adapted to reflect the change in overall Palladium product strategy, to be discussed next.

Palladium “revolution”
As mentioned above, the need for accelerated simulation is reaching lower levels of IP, core, and SoC verification. To enable (and scale) for this growing requirement, Palladium Z1 has been re-designed to be a “data center” resource.

The unique product form factor of previous Palladium models has been replaced by a rack, with footprint, power, cooling, and cabling all consistent with data center “standards”.

Verification job queuing and dispatch on Palladium Z1 integrates readily with existing compute infrastructure (such as the LSF resource management tool).

The allocation of Palladium Z1 capacity to a verification task no longer requires an expert in the Palladium architecture to assign domains to each project. The job allocation to specific Palladium domain(s) is managed by the Cadence software. Indeed, the Z1 resources are dynamically allocated. Re-targeting of job resources is supported — i.e., re-location and re-shaping, without re-compilation — to enable a subsequent large dispatched job to have the (contiguous) resources necessary to execute with optimal performance. Frank indicated that the new platform supports up to 2304 concurrent jobs, with a 4M gate granularity.

As illustrated above, the EDK hardware emulation attach support has also been adapted to the data center strategy, with modules physically accessible to the Palladium Z1 in a rack located within 30 meters. These attached resources are available to verification users across the corporate data center network.

The strategy of expanding simulation acceleration to a much larger set of users and verification tasks also requires addressing the multitude of “usage models” that a verification team encompasses. The figure below highlights the specific areas of focus that Cadence has maintained for the Palladium Z1.

Throughout successive generations of microelectronics technology, the complexity of building block designs has grown, as has their functional verification requirements.

Yet, the transition from software simulation to an accelerated emulation or FPGA prototyping platform has typically required specific expertise, which has hindered the utilization of these platforms across the range of verification tasks. The data center focus of the new Palladium Z1 platform addresses this issue, and significantly reduces the “expertise gap”.

Verification project plans can now incorporate greater diversity in target tools and platforms for each level of design decomposition, to optimize throughput and testbench focus. The impact of adopting accelerated throughput across a wider set of models – especially, IP and subsystem designs – could indeed “revolutionize” how large design projects are verified.

More information on Palladium Z1 is available HERE.

-chipguy