Ultra-Short Reach PHY IP Optimized for Advanced Packaging Technology

Frequent Semiwiki readers are no doubt familiar with the rapid advances in 2.5D heterogeneous multi-die packaging technology.  A relatively well-established product sector utilizing this technology is the 2.5D integration of logic die with a high-bandwidth memory (HBM) DRAM die stack on a silicon interposer;  the interposer is then attached to an organic substrate.  An emerging sector of this packaging technology is the 2.5D integration of multiple die directly on an organic substrate, without the interposer.  The figure below depicts the relative advantages between discrete packages on a PCB, 2.5D multi-die integration with interposer, and multi-die integration directly on the organic substrate. [Reference 1]

The interposer offers optimal coefficient of thermal expansion (CTE) matching and inter-die wiring density, at a significant cost premium.  The multi-die organic substrate solution provides an attractive balance of the five product characteristics at the corners of the pentagon in the figure.

The figures below illustrate cross-sections of these offerings, with an expanded view of the organic package layers. (also from [1])

For the interposer-based solution with processor(s) and HBM die, a wide parallel signal interface is optimal, leveraging the wiring density advantages available with the interposer layers (commonly denoted as a bunch of wires, or BoW).

The applications for direct organic substrate integration are more varied.  As an example, consider a large radix data switching system, where an increased number of ports permits flatter topologies, resulting in less cost while expanding the aggregate bandwidth.  Consider the figure below – a 51.2Tbps switch could be realized by the integration of two principal core chips with additional die providing the off-package SerDes communication.  (Source:  Cadence Design Systems)

A key design consideration is the die-to-die (D2D) interface on the package, highlighted in yellow in the figure above.  The figure below categorizes the technology options to evaluate for the D2D interconnect.  (Source:  Cadence)

A sweet spot for many applications will be the adoption of a non-return-to-zero (NRZ) D2D serial interface.  A parallel interface would be too costly.  The emerging PAM4 serial signaling definition would provide high bandwidth, at the expense of significantly more complex Tx and Rx SerDes circuitry.  The simple NRZ (2-level) serial interface may be appropriate for this class of multi-die packaging.

Parenthetically, there is an engineering assessment used for the NRZ versus PAM4 tradeoff.  The frequency-dependent signal loss for the connection between Tx and Rx is represented by the S-parameter matrix element S21 (assuming a matched impedance throughout the network).  S21 is negative;  its absolute value |S21| is typically referred to as the insertion loss.  The Nyquist frequency for NRZ is one-half the Gbps datarate – e.g., 28Gbps corresponds to a Nyquist frequency of 14GHz.  PAM4 signaling enables doubling the channel data rate without changing the required bandwidth, at the expense of additional SerDes circuit complexity – e.g., 56Gbps PAM4 also corresponds to a Nyquist frequency of 14GHz.  If the data rate were the key design consideration, the PAM4 versus NRZ evaluation is done using the following insertion loss relation:

PAM4 is preferred if:   S21(NRZ_Nyquist) < ( S21(PAM4_Nyquist) – 9.6dB )

In other words, PAM4 requires about 9.6dB more signal-to-noise ratio than NRZ (at their respective Nyquist frequencies), to maintain the same error rate characteristics.

A new type of SerDes has been defined to represent this class of multi-die interface design – an ultra-short reach (USR) serial interface topology.  The critical characteristics of USR serial communications are:

• bandwidth/mm of die-to-die edge interface (Tbps/mm)
• power dissipation (pJ/bit):  e.g., <1 pJ/bit for USR, compared to 6-10 pJ/bit for long-reach interfaces
• latency (nsec):  critical for data switching applications, requiring minimal serial link training time
• bit error rate:  extremely critical, target would be BER < 10**-15;  note that the typical BER for a long-reach (LR) SerDes interface is more on the order of BER~10**-12
• reach:  characterized by the low dB signal insertion loss for the USR distance between Tx and Rx lanes in the D2D configuration of the organic package;   e.g., a interconnect length of ~20-50 mm

For the USR SerDes circuitry, a number of simplifying design selections are made, addressing the requirements above while concurrently optimizing the area and cost:

• a “clock-forwarded” interface is used;  (a divided frequency of) the Tx clock is provided with a set of lanes
• only basic signal equalization is required
• no clock-data recovery (CDR) or forward error correction (FEC) circuitry is included with the Rx design
• NRZ (two-level) signaling is used, rather than PAM4
• the IP supporting the D2D links needs to support multiple system power states
• the IP supporting the D2D links needs to support self-test

The figure below illustrates the simplification of the Tx and Rx SerDes circuitry for the USR design. (from [1])

Another illustration of the USR D2D interface is provided in the figure below – a set of Tx lanes are designed with the clock driver as part of the SerDes IP layout. (Source:  Cadence)  Physical wiring design constraints are applied for the package interconnects between the die.

Cadence has recently announced their UltraLink D2D PHY IP offering, with the following characteristics:

• 7nm process
• 6 lanes per forwarded clock (1/4 rate, with 6 Tx and 6 Rx lanes)
• 20-40 Gbps NRZ PHY
• 1 Tbps/mm bandwidth (aggregate throughput, ~500 Gbps/mm Tx and Rx individually)
• 130um bump pitch on organic substrate
• microbumps also supported for interposer-based packages

The D2D PHY IP is silicon-proven.  Cadence provided the following diagram of the PHY I/O footprint, and a photo of their D2D PHY IP test board.  All the related IP collateral is available, as well – e.g., Verilog-AMS model, IBIS-AMI electrical model, current profile for SoC physical integration.

For more information on the Cadence PHY IP, here are some links:

UltraLink D2D PHY IP:  link

Additional high-performance interface IP:  link

PS.  The standards for ultra-short reach die-to-die SerDes specifications are emerging.  The Optical Internetworking Forum, or OIF, is taking the lead in defining implementation specifications for D2D interfaces.  For more information, refer to the OIP Common Electrical Interface for 112Gbps web page – link.  (Note that OSI refers to this topology as extra-short reach, or XSR.)  Designers may encounter some availability issues with “chiplets” for multi-die integration that support this standard.  The initial product ramp will likely be driven by D2D implementations where the design team owns both sides of the interface, and can utilize USR PHY IP.

-chipguy

[1]  B. Dehlaghi Jadid, “Ultra Short Reach Die-to-Die Links”, Univ. of Toronto, https://tspace.library.utoronto.ca/handle/1807/80831