With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.
This new paradigm of design automation at system level unfolds many opportunities for new players to enter into the semiconductor design world. At the system level, multiple engineering disciplines come together and open possibilities for new learning from different domains and doing things in newer innovative ways. What we call adjacency areas of EDA will eventually become the mainstream of semiconductor design in the form of System Design Automation.
A live example of this is how Vayavya Labs has transformed from what started as an embedded software automation tools to a software-driven verification & validation firm in addition to software device driver automation.
[Vayavya team at their Bangalore office, captured in a selfie]
Vayavya Labs Pvt. Ltd. was founded in 2006 in India with headquarter in Belgaum (Karnataka state in India) and offices in Bangalore and USA. It is privately held and venture funded by India Angel Network (IAN).
[Founding team at Vayavya Labs, (L to R) Venugopal Kolathur, Uma Bondada, RK Patil]
It was a pleasant occasion for me to meet RK Patil, CEO and Co-Founder of Vayavya Labs who provided a great, thoughtful insight into how the executive team at Vayavya manoeuvred the company to expand into a portfolio of technologies that plays in EDA/ESL, semiconductor and embedded software space. Here is the conversation –
Q: RK, How do you explain Vayavya’s existence in electronic industry? It has been there since much before it started in the semiconductor design automation space.
A: We started off in 2006, with a single objective of solving the problems & pains of avoiding buggy software for device drivers in system design. The founding team came mainly from embedded software design & development background. They had seen how system design firms had begun to demand production ready device drivers for different operating systems and platforms (design variants) from their semiconductor suppliers. You can say that this is the effect of what people say “software is feeding the world”. Today the semiconductor and system design firms employ more software engineers than ever and their software spends keep expanding year-on-year. Our collective industry experience in embedded software, system design and semiconductor firms helped us to realize this as an opportunity to provide tools & tool enabled services in the semiconductor enabled electronic world.
Q: So, how did you get the idea of entering into the semiconductor design automation, when the EDA/ESL industry is talking about SHIFT LEFT strategy?
A: Well, Accidental! In a sentence to summarize, we were just apt to do it. Even after ten years we still have to explain (both to our customers & investors!) that Vayavya Labs is at the cusp of three disciplines: Automation-System Design–Embedded Software. While the EDA/ESL fraternity is talking about SHIFT LEFT strategy, strangely for Vayavya Labs the journey began at somewhat RIGHT side of design flow(software world) and we have been progressing LEFT through system-design, software-driven verification and system-level validation.
Vayavya’s core expertise is embedded software. By virtue of being in this domain the team had an opportunity to closely interact with system designers, and many a times being part of the SoC design teams to define software requirements and strategies. Very often we have seen (for the same SoC) customers coming back to semiconductor firms asking for software that would meet their application requirements even though the SoC firm had already supplied the reference software. Also, internally within the SoC firm, there are several iterations between software/firmware team, test & verification team, and design & verification team to clarify functional behaviour of a device.
What we observed is that there is lot of commonality between all these activities being done in disjoint manner by different teams. The functional tests carried out in simulation and emulation environments can very well relate with post silicon bring up and bare metal driver writing activities. The implementation domains and languages used might be different, but essentially they are to test the same functional aspect of a design under different environments.
This led us to think that there could be a better way to address these challenges. Formal and high level specifications coupled with design automation tools were natural ways to solve this problem and there started the journey of Vayavya Labs.
When the semiconductor world started transforming into SoCs and IP-integration play, we saw this as an opportune time to use our expertise in providing solutions for systems in the semiconductor domain. Vayavya Labs filed several patents in its early part of the journey and started building tools based on those patents and piloting the tools to fit into the existing SoC design flows.
Over the years we have provided consultancy and design/development services for software to leading semiconductor, SoC IP, and system design companies. Our team has gained deep expertise and valuable insight into system modelling, hardware-software co-design and verification, embedded software, and so on. It is this unique expertise and experience that helps us to conceive tools & methodologies.
Q: That’s impressive. Can you tell us more about DDGen, your flagship product for Device Driver Automation?
A: The acronym ‘DDGen’ is for Device Driver Generator, our flagship product for automation of software device drivers. As I mentioned earlier, our topmost objective to start with was to address the pain points and technical-skills associated with Device Driver development, thereby saving SoC providers from delays due to non-availability or complexity of device driver implementation.
Because of our deep expertise & experience in driver development (a variety of them, from simple to most complex), we were able to define and classify most of the software drivers in the industry into a sub-set of driver models, and map the device driver development activity into an automated process. Interestingly, we borrowed the concepts of high-level-synthesis (HLS) from EDA world and applied it to the software domain.
DDGen tool is already in the field and is deployed at some of our leading IP and SoC customers. We are in the process of making this tool available as a Platform-as-a-Service (PaaS). You could get a glimpse of things to come at http://devicedrivers.org/
Q: O.K. Of late there is a lot of news and talk around scenario-driven test methodology. That also reminds me about Vayavya’s recent involvement in Accellera’s Portable Stimulus Working Group (PSWG) activities. Would you like to elaborate a little on that involvement? How did it happen?
A: As I said earlier Vayavya Labs is an outsider in EDA domain. Probably that is the reason we tend to look at this domain in a very different way. We have worked with diverse set of companies providing solutions for hardware-software interfaces, embedded systems, device drivers and Operating System (OS) porting. What we discovered is that every device in multiple verticals (application areas) needed a different driver to work under different operating systems. And the device drivers were developed afresh by different teams.
As stated earlier, we observed lot of duplication of effort between multiple teams in different verticals whereas the underlying principles (device set up, access, response) were same for each of these drivers. This was an opportunity for us to optimize resources in each of these verticals by standardizing hardware/software interfaces.
So we developed common specifications for device programming and run time operating environment. These specifications are then input to a decision-making and generator engine (aka a smart high level compiler and generator) to automatically generate device drivers for target operating environments. The idea was to simplify and segregate the hardware team to specify the Device Programming Sequence (DPS) and software team to define the Runtime Specification (RTS) for a device, and leave the rest to our software tool (Hardware/Software Interface Compiler) to automatically generate the appropriate driver for a particular device under target operating environment.
While we were championing the idea of demystifying “Device Driver Writing” all through 2011-2014 it never occurred to us that there was a parallel industry move, mainly from SoC verification & validation teams rallying for “Portable Stimulus”. During this time, it was a nice opportunity when Accellera announced the formation of Portable Stimulus Working Group (PSWG). So, we became a contributing member to PSWG.
We believe that the standardization efforts of PSWG will eventually help in establishing software-driven verification methodology for SoCs which opens up a totally new paradigm in SoC verification space. It will promote seamless interoperability between different verification engines, and also reuse of testcases and test infrastructure at different levels of abstractions of SoCs. This will eliminate major duplication of efforts in SoC verification space, and also automate the overall space.
Q: This is an excellent contribution from Vayavya into the SoC verification community. What kind of time horizon you can foresee for the software or scenario driven verification to come in the mainstream of SoC verification?
A: I would say it is happening now. While a lot depends on ratification of standards and eventually going through the IEEE process, I believe in this year Accellera might have a consensus on the standards and a formal draft of the specs should be in place. While all this happens on the standards front, one can anticipate the early movers in this field to engage with alpha/beta customers. If everything goes well then the first set of tools integrated into design flows and customer success stories should become the newsmakers by early 2018.
Q: What are your future plans for semiconductor design automation?
A: In our view, the Hardware-Software Interface specification (HSI) will become the central theme for modern SoC design, verification, validation and software development flow. While we contribute & work for standardization efforts we are also committed to see how our tools & technologies seamlessly integrate with existing EDA/ESL tools and flows which are deployed in the semiconductor design houses.
Our immediate focus is to see proliferation of high level specs as part of semiconductor IP, SoC design & verification, and embedded software activities. Once the high level specs are in place the new generation of tools would automate things like software-driven verification, Hybrid/Accelerated verification, driver automation, and so on.
A bigger and grandeur vision is to realise “Just-In-Time-Driver” concept. Here, the device drivers for any design and a host of operating systems (Run Time Environments) can be generated on the fly as a system designer identifies components from a library and goes about designing a system. The generated device drivers can be rebuilt with any boot image or operating system libraries. In this way the hardware (platform design) and the operating systems can evolve (revisions/updates) at their own pace and timelines.
To summarize, I would say we are in an interesting and exciting space & time.
This was a very intriguing discussion with RK. The team at Vayavya is superb and they understand very well what they are doing. They have wide exposure from different segments of modern electronic industry and this is proving very beneficial for them in doing the right things for System Design Automation in the semiconductor space.
Share this post via:
TSMC Unveils the World’s Most Advanced Logic Technology at IEDM