Accelerating Analog Signoff with Parasitics

An under-appreciated but critical component in signing off the final stage of chip design for manufacture is timing closure – aligning accurate timing based on final physical implementation with the product specification. Between advanced manufacturing processes and growing design sizes, the most important factors determining timing – interconnect resistance and capacitance parasitics – have become more and more difficult to estimate accurately before final layout. Which is a problem since unexpected variances may require expensive rework at a time when the product schedule calls for speedy transition to manufacturing handoff.

Digital design flows have largely compensated for such variances through further automation and improved virtual modeling of likely interconnect topologies. Following pre-signoff analyses, designers can be reasonably sure that necessary post-layout ECOs, if any, should be relatively limited and easy to fix. Not so in analog (also mixed signal and RF). According to Hao Ji (VP R&D at Cadence, particularly responsible for parasitic extraction) and Akshat Shah (Sr. PE Group Director for the Virtuoso Platform at Cadence), analog design lacks the heavy automation common in digital flows and still depends heavily on handcrafted layouts guided by hand-estimated parasitics. As a result, while earlier generation analog post-layout sims might also have converged quickly, now they never work first time.

This challenge for analog closure is not a minor issue. Surveys indicate that drivers for silicon respins are now dominated by analog issues, not surprising since analog now plays a growing role in almost all large chip-designs – in PCIe, DDR/HBM and Ethernet interfaces, also in sensing. All domains on which modern systems advances critically depend.

Differences between estimated and real extracted parasitics can commonly take 6-8 weeks to diagnose and resolve, at a time when the pressure to tapeout is most intense. To squeeze this time, solutions must accommodate to the unique challenges of analog, helping to accelerate expert designer insight and suggested fixes before starting long-cycle layout changes and re-simulation. That’s what the Cadence Quantus^TM  Insight Solution offers.

What makes analog post-layout signoff so difficult?

Part of the problem is simply the cycle time to make and re-verify changes: updating the schematic/layout, re-verifying through LVS, then re-verifying through SPICE(or other) simulation. This is a much slower cycle than hand-tweaking a digital netlist and re-running logic simulation, especially since even the fastest modern circuit simulators run 2-3 orders of magnitude slower than a (software) logic simulator.

A circuit designer suggests constraints to guide a layout designer, such as “make this connection no more than 10 ohms”. For the layout designer this advice is an approximate guideline since the complexity of routing through multiple layers and vias makes both resistance and capacitance hard to estimate. The layout designer will do their best, a very short route perhaps, but it won’t match the constraint precisely.

More generally, resistances in an advanced process have become critically important and are very hard to estimate in complex topology nets traversing through multiple layers of interconnect and vias. Field solvers are needed to determine accurate values so it shouldn’t be surprising that back-of-the-envelope calculations may be quite far off. Common fixes to address high resistance paths are known, for example arrayed vias or parallel routing paths. But first you need to know where such fixes might be needed.

Differential pairs present another challenge, in some ways easier to manage in layout because the layout designer knows that such connections must be exactly symmetric. But what isn’t easy to account for is capacitance contributions from neighboring wires, or from metal fills which don’t respect symmetry. Those effects aren’t going to be clear until post-layout extraction.

Diagnosing and determining optimal solutions to such problems depends on the judgement of expert designers. For now at least this judgement can’t be automated away, however automation can simplify debug and trial fixes. This is where the Quantus Insight Solution can help.

The path to diagnosis and what-if experiments

According to Hao, a DSPF extracted from a circuit of 100k instances can run to more than tens of millions of parasitic elements. The DSPF is an ASCII file, clearly at this scale completely unmanageable for manual analysis. Quantus Insight Solution bridges this gap by acting as a visual interactive DSPF debugger, coupled with Virtuoso schematic and layout views.

Suppose you know roughly where to look for a problem. You can zoom in on schematic or layout views to see overlaid resistance, capacitance or estimated (Elmore) delay values for point-to-point connections or layer-wise splits of a net. These are visualized as sorted tables (of R, C or delay), highest values first together with a heatmap representation of corresponding parasitic nets. From this view it’s often quite easy to see why the implemented layout deviates from the spec, for example in an R segment perhaps exceeding the constraint for the whole net, also to see which layer (or via) contributed significantly to that problem.

Sometimes the root cause for an error won’t be quite so obvious; say a differential pair fails to match but there are no standout culprits in either R or C. This is where Elmore delay estimates can be helpful, to highlight cumulative deviations in matching the pair.

If you don’t have a starting point, you can compare with the constraints set to guide layout, or you can compare 2 DSPFs, perhaps one working and one not working, to quickly isolate problem areas. For example if a capacitance is much higher than expected you can see exactly which layer contributed to that excess.

Then you can run a what-if analysis on changes you think may correct a problem. For example, you might change a resistance component and ask to recompute effective resistance to get a first order sense of whether that resolves the issue. If that fix looks good, Quantus Insight Solution can quickly generate a new DSPF on which you can re-run (SPICE) simulation to further verify suitability of the fix. In this way you can iterate relatively quickly through open issues. Only when satisfied do you need to go back to the layout designer to implement your suggested fixes.

You can learn more HERE.