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Partitioning Pavilion Panel

Partitioning Pavilion Panel
by Paul McLellan on 05-28-2012 at 6:27 pm

 I don’t think it can be a surprise to anyone reading this that designs have been getting larger. Someone called Moore said something about it decades ago, or so I heard. Designs are so large that they need to be partitioned into smaller parts. The two main motivations for this are that some design tools, especially place & route, cannot handle a whole modern design flat, and secondly, it makes sense to split up a design when different parts are being handled by different teams especially if they are geographically dispersed.

Doing the minimum amount of partitioning such that the design can still run through the design flow is one end of the scale. But it may be suboptimum. You may require very long runtimes on your largest servers and more partitioning would result in a faster iteration loop for the slow running steps. Plus the project management may be tricky if you have more design teams than partitions. On the other hand, partitioning down into tiny blocks, perhaps one block per designer, is suboptimal. You always lose something at the boundaries when you partition and so doing it excessively results in losing too much. There is a sense in which you want to run the design as flat as possible and the art comes into deciding just what ‘as flat as possible’ really means. It depends on details of tools, design teams, existing IP, future anticipated re-use, company culture and probably some more things that don’t come to mind right now.

There is a panel session at DAC called Divide and Conquer—Intelligent Partitioning from 1.30pm to 2.15pm on Wednesday June 6th. It is at the DAC Pavilion in the exhibit hall, which is also booth 310. I shall certainly be there.

Wait…I shall certainly be there since I’m the moderator. The panelists are Santosh Santosh of NVIDIA in Santa Clara, Jonathan DeMent from IBM in Austin and Hao Nham from eSilicon in Santa Clara. Their different backgrounds will make for an interesting discussion. IBM and NVIDIA tend to be working on one huge design at a time, whereas eSilicon does dozens a year since they are a fabless ASIC business. We had a conference call a couple of weeks ago and everyone was already off arguing and I had to shut them down so we could discuss the logistics and so that they didn’t use up all the good material before the audience arrived.

The DAC website page about the panel is here.

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